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LibC: Implement fenv.h
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Userland/Libraries/LibC/fenv.cpp
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Userland/Libraries/LibC/fenv.cpp
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/*
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* Copyright (c) 2021, Mițca Dumitru <dumitru0mitca@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/Types.h>
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#include <fenv.h>
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// This is the size of the floating point envinronment image in protected mode
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static_assert(sizeof(__x87_floating_point_environment) == 28);
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static u16 read_status_register()
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{
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u16 status_register;
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asm volatile("fstsw %0"
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: "=m"(status_register));
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return status_register;
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}
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static u16 read_control_word()
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{
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u16 control_word;
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asm volatile("fstcw %0"
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: "=m"(control_word));
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return control_word;
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}
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static void set_control_word(u16 new_control_word)
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{
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asm volatile("fldcw %0" ::"m"(new_control_word));
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}
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static u32 read_mxcsr()
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{
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u32 mxcsr;
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asm volatile("stmxcsr %0"
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: "=m"(mxcsr));
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return mxcsr;
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}
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static void set_mxcsr(u32 new_mxcsr)
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{
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asm volatile("ldmxcsr %0" ::"m"(new_mxcsr));
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}
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static constexpr u32 default_mxcsr_value = 0x1f80;
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extern "C" {
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int fegetenv(fenv_t* env)
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{
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if (!env)
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return 1;
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asm volatile("fstenv %0"
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: "=m"(env->__x87_fpu_env)::"memory");
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env->__mxcsr = read_mxcsr();
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return 0;
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}
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int fesetenv(const fenv_t* env)
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{
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if (!env)
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return 1;
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if (env == FE_DFL_ENV) {
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asm volatile("finit");
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set_mxcsr(default_mxcsr_value);
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return 0;
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}
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asm volatile("fldenv %0" ::"m"(env)
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: "memory");
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set_mxcsr(env->__mxcsr);
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return 0;
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}
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int feholdexcept(fenv_t* env)
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{
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fegetenv(env);
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fenv_t current_env;
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fegetenv(¤t_env);
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current_env.__x87_fpu_env.__status_word &= ~FE_ALL_EXCEPT;
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current_env.__x87_fpu_env.__status_word &= ~(1 << 7); // Clear the "Exception Status Summary" bit
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current_env.__x87_fpu_env.__control_word &= FE_ALL_EXCEPT; // Masking these bits stops the corresponding exceptions from being generated according to the Intel Programmer's Manual
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fesetenv(¤t_env);
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return 0;
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}
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int feupdateenv(const fenv_t* env)
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{
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auto currently_raised_exceptions = fetestexcept(FE_ALL_EXCEPT);
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fesetenv(env);
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feraiseexcept(currently_raised_exceptions);
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return 0;
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}
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int fegetexceptflag(fexcept_t* except, int exceptions)
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{
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if (!except)
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return 1;
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*except = (uint16_t)fetestexcept(exceptions);
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return 0;
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}
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int fesetexceptflag(const fexcept_t* except, int exceptions)
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{
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if (!except)
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return 1;
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fenv_t current_env;
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fegetenv(¤t_env);
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exceptions &= FE_ALL_EXCEPT;
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current_env.__x87_fpu_env.__status_word &= exceptions;
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current_env.__x87_fpu_env.__status_word &= ~(1 << 7); // Make sure exceptions don't get raised
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fesetenv(¤t_env);
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return 0;
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}
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int fegetround()
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{
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// There's no way to signal whether the SSE rounding mode and x87 ones are different, so we assume they're the same
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return (read_status_register() >> 10) & 3;
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}
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int fesetround(int rounding_mode)
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{
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if (rounding_mode < FE_TONEAREST || rounding_mode > FE_TOWARDSZERO)
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return 1;
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auto control_word = read_control_word();
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control_word &= ~(3 << 10);
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control_word |= rounding_mode << 10;
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set_control_word(control_word);
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auto mxcsr = read_mxcsr();
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mxcsr &= ~(3 << 13);
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mxcsr |= rounding_mode << 13;
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set_mxcsr(mxcsr);
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return 0;
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}
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int feclearexcepts(int exceptions)
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{
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exceptions &= FE_ALL_EXCEPT;
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fenv_t current_env;
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fegetenv(¤t_env);
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current_env.__x87_fpu_env.__status_word &= ~exceptions;
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current_env.__x87_fpu_env.__status_word &= ~(1 << 7); // Clear the "Exception Status Summary" bit
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fesetenv(¤t_env);
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return 0;
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}
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int fetestexcept(int exceptions)
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{
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u16 status_register = read_status_register() & FE_ALL_EXCEPT;
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exceptions &= FE_ALL_EXCEPT;
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return status_register & exceptions;
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}
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int feraiseexcept(int exceptions)
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{
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fenv_t env;
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fegetenv(&env);
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exceptions &= FE_ALL_EXCEPT;
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// While the order in which the exceptions is raised is unspecified, FE_OVERFLOW and FE_UNDERFLOW must be raised before FE_INEXACT, so handle that case in this branch
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if (exceptions & FE_INEXACT) {
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env.__x87_fpu_env.__status_word &= ((u16)exceptions & ~FE_INEXACT);
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fesetenv(&env);
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asm volatile("fwait"); // "raise" the exception by performing a floating point operation
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fegetenv(&env);
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env.__x87_fpu_env.__status_word &= FE_INEXACT;
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fesetenv(&env);
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asm volatile("fwait");
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return 0;
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}
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env.__x87_fpu_env.__status_word &= exceptions;
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fesetenv(&env);
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asm volatile("fwait");
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return 0;
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}
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}
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