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UserspaceEmulator: Implement the SAR instruction

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Let's try doing this with some inline assembly. We know we're running
on an x86 target anyway. :^)
This commit is contained in:
Andreas Kling 2020-07-10 20:15:53 +02:00
parent 3899effb19
commit 04d58f54b3
2 changed files with 118 additions and 28 deletions
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83
DevTools/UserspaceEmulator/SoftCPU.cpp
View file

@ -652,15 +652,80 @@ void SoftCPU::ROR_RM8_CL(const X86::Instruction&) { TODO(); }
void SoftCPU::ROR_RM8_imm8(const X86::Instruction&) { TODO(); }
void SoftCPU::SAHF(const X86::Instruction&) { TODO(); }
void SoftCPU::SALC(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM16_1(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM16_CL(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM16_imm8(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM32_1(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM32_CL(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM32_imm8(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM8_1(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM8_CL(const X86::Instruction&) { TODO(); }
void SoftCPU::SAR_RM8_imm8(const X86::Instruction&) { TODO(); }
template<typename T>
T SoftCPU::sar_impl(T data, u8 steps)
{
if (steps == 0)
return data;
u32 result = 0;
u32 new_flags = 0;
asm("sarl %%cl, %%eax\n"
"mov %%eax, %%ebx\n"
"pushf\n"
"pop %%eax\n"
: "=a"(new_flags), "=b"(result)
: "a"(data), "c"(steps));
set_flags_oszapc(new_flags);
return result;
}
void SoftCPU::SAR_RM16_1(const X86::Instruction& insn)
{
auto data = insn.modrm().read16(*this, insn);
insn.modrm().write16(*this, insn, sar_impl(data, 1));
}
void SoftCPU::SAR_RM16_CL(const X86::Instruction& insn)
{
auto data = insn.modrm().read16(*this, insn);
insn.modrm().write16(*this, insn, sar_impl(data, cl()));
}
void SoftCPU::SAR_RM16_imm8(const X86::Instruction& insn)
{
auto data = insn.modrm().read16(*this, insn);
insn.modrm().write16(*this, insn, sar_impl(data, insn.imm8()));
}
void SoftCPU::SAR_RM32_1(const X86::Instruction& insn)
{
auto data = insn.modrm().read32(*this, insn);
insn.modrm().write32(*this, insn, sar_impl(data, 1));
}
void SoftCPU::SAR_RM32_CL(const X86::Instruction& insn)
{
auto data = insn.modrm().read32(*this, insn);
insn.modrm().write32(*this, insn, sar_impl(data, cl()));
}
void SoftCPU::SAR_RM32_imm8(const X86::Instruction& insn)
{
auto data = insn.modrm().read32(*this, insn);
insn.modrm().write32(*this, insn, sar_impl(data, insn.imm8()));
}
void SoftCPU::SAR_RM8_1(const X86::Instruction& insn)
{
auto data = insn.modrm().read8(*this, insn);
insn.modrm().write8(*this, insn, sar_impl(data, 1));
}
void SoftCPU::SAR_RM8_CL(const X86::Instruction& insn)
{
auto data = insn.modrm().read8(*this, insn);
insn.modrm().write8(*this, insn, sar_impl(data, cl()));
}
void SoftCPU::SAR_RM8_imm8(const X86::Instruction& insn)
{
auto data = insn.modrm().read8(*this, insn);
insn.modrm().write8(*this, insn, sar_impl(data, insn.imm8()));
}
void SoftCPU::SBB_AL_imm8(const X86::Instruction&) { TODO(); }
void SoftCPU::SBB_AX_imm16(const X86::Instruction&) { TODO(); }
void SoftCPU::SBB_EAX_imm32(const X86::Instruction&) { TODO(); }

63
DevTools/UserspaceEmulator/SoftCPU.h
View file

@ -53,6 +53,20 @@ public:
explicit SoftCPU(Emulator&);
void dump() const;
struct Flags {
enum Flag {
CF = 0x0001,
PF = 0x0004,
AF = 0x0010,
ZF = 0x0040,
SF = 0x0080,
TF = 0x0100,
IF = 0x0200,
DF = 0x0400,
OF = 0x0800,
};
};
void push32(u32);
u32 pop32();
@ -165,19 +179,27 @@ public:
void set_dl(u8 value) { gpr8(X86::RegisterDL) = value; }
void set_dh(u8 value) { gpr8(X86::RegisterDH) = value; }
bool of() const { return m_of; }
bool sf() const { return m_sf; }
bool zf() const { return m_zf; }
bool af() const { return m_af; }
bool pf() const { return m_pf; }
bool cf() const { return m_cf; }
bool of() const { return m_eflags & Flags::OF; }
bool sf() const { return m_eflags & Flags::SF; }
bool zf() const { return m_eflags & Flags::ZF; }
bool af() const { return m_eflags & Flags::AF; }
bool pf() const { return m_eflags & Flags::PF; }
bool cf() const { return m_eflags & Flags::CF; }
void set_of(bool value) { m_of = value; }
void set_sf(bool value) { m_sf = value; }
void set_zf(bool value) { m_zf = value; }
void set_af(bool value) { m_af = value; }
void set_pf(bool value) { m_pf = value; }
void set_cf(bool value) { m_cf = value; }
void set_flag(Flags::Flag flag, bool value)
{
if (value)
m_eflags |= flag;
else
m_eflags &= ~flag;
}
void set_of(bool value) { set_flag(Flags::OF, value); }
void set_sf(bool value) { set_flag(Flags::SF, value); }
void set_zf(bool value) { set_flag(Flags::ZF, value); }
void set_af(bool value) { set_flag(Flags::AF, value); }
void set_pf(bool value) { set_flag(Flags::PF, value); }
void set_cf(bool value) { set_flag(Flags::CF, value); }
u16 cs() const { return m_segment[(int)X86::SegmentRegister::CS]; }
u16 ds() const { return m_segment[(int)X86::SegmentRegister::DS]; }
@ -692,18 +714,21 @@ private:
template<typename Op>
void generic_reg8_RM8(Op, const X86::Instruction&);
template<typename T>
T sar_impl(T data, u8 steps);
void set_flags_oszapc(u32 new_flags)
{
m_eflags &= ~(Flags::OF | Flags::SF | Flags::ZF | Flags::AF | Flags::PF | Flags::CF);
m_eflags |= new_flags & (Flags::OF | Flags::SF | Flags::ZF | Flags::AF | Flags::PF | Flags::CF);
}
private:
Emulator& m_emulator;
PartAddressableRegister m_gpr[8];
u16 m_segment[8] { 0 };
bool m_of { false };
bool m_sf { false };
bool m_zf { false };
bool m_af { false };
bool m_pf { false };
bool m_cf { false };
u32 m_eflags { 0 };
};
}