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Kernel: Introduce the IOWindow class

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This class is intended to replace all IOAddress usages in the Kernel
codebase altogether. The idea is to ensure IO can be done in
arch-specific manner that is determined mostly in compile-time, but to
still be able to use most of the Kernel code in non-x86 builds. Specific
devices that rely on x86-specific IO instructions are already placed in
the Arch/x86 directory and are omitted for non-x86 builds.

The reason this works so well is the fact that x86 IO space acts in a
similar fashion to the traditional memory space being available in most
CPU architectures - the x86 IO space is essentially just an array of
bytes like the physical memory address space, but requires x86 IO
instructions to load and store data. Therefore, many devices allow host
software to interact with the hardware registers in both ways, with a
noticeable trend even in the modern x86 hardware to move away from the
old x86 IO space to exclusively using memory-mapped IO.

Therefore, the IOWindow class encapsulates both methods for x86 builds.
The idea is to allow PCI devices to be used in either way in x86 builds,
so when trying to map an IOWindow on a PCI BAR, the Kernel will try to
find the proper method being declared with the PCI BAR flags.
For old PCI hardware on non-x86 builds this might turn into a problem as
we can't use port mapped IO, so the Kernel will gracefully fail with
ENOTSUP error code if that's the case, as there's really nothing we can
do within such case.

For general IO, the read{8,16,32} and write{8,16,32} methods are
available as a convenient API for other places in the Kernel. There are
simply no direct 64-bit IO API methods yet, as it's not needed right now
and is not considered to be Arch-agnostic too - the x86 IO space doesn't
support generating 64 bit cycle on IO bus and instead requires two 2
32-bit accesses. If for whatever reason it appears to be necessary to do
IO in such manner, it could probably be added with some neat tricks to
do so. It is recommended to use Memory::TypedMapping struct if direct 64
bit IO is actually needed.
This commit is contained in:
Liav A 2022-09-23 11:50:04 +03:00 • committed by Linus Groh
parent 6bafbd64e2
commit 05ba034000
36 changed files with 919 additions and 469 deletions
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77
Kernel/Bus/VirtIO/Device.cpp
View file

@ -90,8 +90,6 @@ UNMAP_AFTER_INIT void Device::initialize()
{
auto address = pci_address();
enable_bus_mastering(pci_address());
PCI::enable_interrupt_line(pci_address());
enable_irq();
auto capabilities = PCI::get_device_identifier(address).capabilities();
for (auto& capability : capabilities) {
@ -128,27 +126,23 @@ UNMAP_AFTER_INIT void Device::initialize()
if (m_use_mmio) {
for (auto& cfg : m_configs) {
auto& mapping = m_mmio[cfg.bar];
mapping.size = PCI::get_BAR_space_size(pci_address(), static_cast<PCI::HeaderType0BaseRegister>(cfg.bar));
if (!mapping.base && mapping.size) {
auto region_size_or_error = Memory::page_round_up(mapping.size);
if (region_size_or_error.is_error()) {
dbgln_if(VIRTIO_DEBUG, "{}: Failed to round up size={} to pages", m_class_name, mapping.size);
continue;
}
auto region_or_error = MM.allocate_kernel_region(PhysicalAddress(page_base_of(PCI::get_BAR(pci_address(), static_cast<PCI::HeaderType0BaseRegister>(cfg.bar)))), region_size_or_error.value(), "VirtIO MMIO"sv, Memory::Region::Access::ReadWrite, Memory::Region::Cacheable::No);
if (region_or_error.is_error()) {
dbgln_if(VIRTIO_DEBUG, "{}: Failed to map bar {} - (size={}) {}", m_class_name, cfg.bar, mapping.size, region_or_error.error());
} else {
mapping.base = region_or_error.release_value();
}
}
auto mapping_io_window = IOWindow::create_for_pci_device_bar(pci_address(), static_cast<PCI::HeaderType0BaseRegister>(cfg.bar)).release_value_but_fixme_should_propagate_errors();
m_register_bases[cfg.bar] = move(mapping_io_window);
}
m_common_cfg = get_config(ConfigurationType::Common, 0);
m_notify_cfg = get_config(ConfigurationType::Notify, 0);
m_isr_cfg = get_config(ConfigurationType::ISR, 0);
} else {
auto mapping_io_window = IOWindow::create_for_pci_device_bar(pci_address(), PCI::HeaderType0BaseRegister::BAR0).release_value_but_fixme_should_propagate_errors();
m_register_bases[0] = move(mapping_io_window);
}
// Note: We enable interrupts at least after the m_register_bases[0] ptr is
// assigned with an IOWindow, to ensure that in case of getting an interrupt
// we can access registers from that IO window range.
PCI::enable_interrupt_line(pci_address());
enable_irq();
reset_device();
set_status_bit(DEVICE_STATUS_ACKNOWLEDGE);
@ -158,66 +152,67 @@ UNMAP_AFTER_INIT void Device::initialize()
UNMAP_AFTER_INIT VirtIO::Device::Device(PCI::DeviceIdentifier const& device_identifier)
: PCI::Device(device_identifier.address())
, IRQHandler(device_identifier.interrupt_line().value())
, m_io_base(IOAddress(PCI::get_BAR0(pci_address()) & ~1))
, m_class_name(VirtIO::determine_device_class(device_identifier))
{
dbgln("{}: Found @ {}", m_class_name, pci_address());
}
auto Device::mapping_for_bar(u8 bar) -> MappedMMIO&
{
VERIFY(m_use_mmio);
return m_mmio[bar];
}
void Device::notify_queue(u16 queue_index)
{
dbgln_if(VIRTIO_DEBUG, "{}: notifying about queue change at idx: {}", m_class_name, queue_index);
if (!m_notify_cfg)
out<u16>(REG_QUEUE_NOTIFY, queue_index);
base_io_window().write16(REG_QUEUE_NOTIFY, queue_index);
else
config_write16(*m_notify_cfg, get_queue(queue_index).notify_offset() * m_notify_multiplier, queue_index);
}
auto Device::mapping_for_bar(u8 bar) -> IOWindow&
{
VERIFY(m_use_mmio);
VERIFY(m_register_bases[bar]);
return *m_register_bases[bar];
}
u8 Device::config_read8(Configuration const& config, u32 offset)
{
return mapping_for_bar(config.bar).read<u8>(config.offset + offset);
return mapping_for_bar(config.bar).read8(config.offset + offset);
}
u16 Device::config_read16(Configuration const& config, u32 offset)
{
return mapping_for_bar(config.bar).read<u16>(config.offset + offset);
return mapping_for_bar(config.bar).read16(config.offset + offset);
}
u32 Device::config_read32(Configuration const& config, u32 offset)
{
return mapping_for_bar(config.bar).read<u32>(config.offset + offset);
return mapping_for_bar(config.bar).read32(config.offset + offset);
}
void Device::config_write8(Configuration const& config, u32 offset, u8 value)
{
mapping_for_bar(config.bar).write(config.offset + offset, value);
mapping_for_bar(config.bar).write8(config.offset + offset, value);
}
void Device::config_write16(Configuration const& config, u32 offset, u16 value)
{
mapping_for_bar(config.bar).write(config.offset + offset, value);
mapping_for_bar(config.bar).write16(config.offset + offset, value);
}
void Device::config_write32(Configuration const& config, u32 offset, u32 value)
{
mapping_for_bar(config.bar).write(config.offset + offset, value);
mapping_for_bar(config.bar).write32(config.offset + offset, value);
}
void Device::config_write64(Configuration const& config, u32 offset, u64 value)
{
mapping_for_bar(config.bar).write(config.offset + offset, value);
mapping_for_bar(config.bar).write32(config.offset + offset, (u32)(value & 0xFFFFFFFF));
mapping_for_bar(config.bar).write32(config.offset + offset + 4, (u32)(value >> 32));
}
u8 Device::read_status_bits()
{
if (!m_common_cfg)
return in<u8>(REG_DEVICE_STATUS);
return base_io_window().read8(REG_DEVICE_STATUS);
return config_read8(*m_common_cfg, COMMON_CFG_DEVICE_STATUS);
}
@ -225,7 +220,7 @@ void Device::mask_status_bits(u8 status_mask)
{
m_status &= status_mask;
if (!m_common_cfg)
out<u8>(REG_DEVICE_STATUS, m_status);
base_io_window().write8(REG_DEVICE_STATUS, m_status);
else
config_write8(*m_common_cfg, COMMON_CFG_DEVICE_STATUS, m_status);
}
@ -234,7 +229,7 @@ void Device::set_status_bit(u8 status_bit)
{
m_status |= status_bit;
if (!m_common_cfg)
out<u8>(REG_DEVICE_STATUS, m_status);
base_io_window().write8(REG_DEVICE_STATUS, m_status);
else
config_write8(*m_common_cfg, COMMON_CFG_DEVICE_STATUS, m_status);
}
@ -242,7 +237,7 @@ void Device::set_status_bit(u8 status_bit)
u64 Device::get_device_features()
{
if (!m_common_cfg)
return in<u32>(REG_DEVICE_FEATURES);
return base_io_window().read32(REG_DEVICE_FEATURES);
config_write32(*m_common_cfg, COMMON_CFG_DEVICE_FEATURE_SELECT, 0);
auto lower_bits = config_read32(*m_common_cfg, COMMON_CFG_DEVICE_FEATURE);
config_write32(*m_common_cfg, COMMON_CFG_DEVICE_FEATURE_SELECT, 1);
@ -250,6 +245,12 @@ u64 Device::get_device_features()
return upper_bits | lower_bits;
}
IOWindow& Device::base_io_window()
{
VERIFY(m_register_bases[0]);
return *m_register_bases[0];
}
bool Device::accept_device_features(u64 device_features, u64 accepted_features)
{
VERIFY(!m_did_accept_features);
@ -277,7 +278,7 @@ bool Device::accept_device_features(u64 device_features, u64 accepted_features)
dbgln_if(VIRTIO_DEBUG, "{}: Accepted features: {}", m_class_name, accepted_features);
if (!m_common_cfg) {
out<u32>(REG_GUEST_FEATURES, accepted_features);
base_io_window().write32(REG_GUEST_FEATURES, accepted_features);
} else {
config_write32(*m_common_cfg, COMMON_CFG_DRIVER_FEATURE_SELECT, 0);
config_write32(*m_common_cfg, COMMON_CFG_DRIVER_FEATURE, accepted_features);
@ -399,7 +400,7 @@ void Device::finish_init()
u8 Device::isr_status()
{
if (!m_isr_cfg)
return in<u8>(REG_ISR_STATUS);
return base_io_window().read8(REG_ISR_STATUS);
return config_read8(*m_isr_cfg, 0);
}