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Kernel: Set up initial exception stack when going into EL1 on aarch64

When an exception is triggered on aarch64, the processor always switches
to the exception stack which is defined by the SP_EL1 register.
This commit is contained in:
Timon Kruiper 2022-05-10 22:07:42 +02:00 committed by Linus Groh
parent 9f730fab8d
commit 06432719fd
2 changed files with 9 additions and 0 deletions

View file

@ -23,6 +23,11 @@ inline void set_ttbr0_el1(FlatPtr ttbr0_el1)
asm("msr ttbr0_el1, %[value]" ::[value] "r"(ttbr0_el1));
}
inline void set_sp_el1(FlatPtr sp_el1)
{
asm("msr sp_el1, %[value]" ::[value] "r"(sp_el1));
}
inline void flush()
{
asm("dsb ish");

View file

@ -46,6 +46,10 @@ static void drop_to_el1()
hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2);
// Set up initial exception stack
// FIXME: Define in linker script
Aarch64::Asm::set_sp_el1(0x40000);
Aarch64::SPSR_EL2 saved_program_status_register_el2 = {};
// Mask (disable) all interrupts