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LibX86: Add {Address,Operand}Size::Size64

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For now the opcode tables for OperandSize::Size64 are empty
This commit is contained in:
Simon Wanner 2022-03-25 00:08:40 +01:00 • committed by Andreas Kling
parent a7268c3c74
commit 06ece474e9
4 changed files with 98 additions and 11 deletions
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9
Userland/DevTools/UserspaceEmulator/SoftCPU.h
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@ -106,8 +106,9 @@ public:
return m_gpr[X86::RegisterEDX].reference_to<&PartAddressableRegister::low_u8>();
case X86::RegisterDH:
return m_gpr[X86::RegisterEDX].reference_to<&PartAddressableRegister::high_u8>();
default:
VERIFY_NOT_REACHED();
}
VERIFY_NOT_REACHED();
}
ValueWithShadow<u8> const_gpr8(X86::RegisterIndex8 reg) const
@ -129,8 +130,9 @@ public:
return m_gpr[X86::RegisterEDX].slice<&PartAddressableRegister::low_u8>();
case X86::RegisterDH:
return m_gpr[X86::RegisterEDX].slice<&PartAddressableRegister::high_u8>();
default:
VERIFY_NOT_REACHED();
}
VERIFY_NOT_REACHED();
}
ValueWithShadow<u16> const_gpr16(X86::RegisterIndex16 reg) const
@ -211,8 +213,9 @@ public:
case X86::AddressSize::Size16:
set_cx(ValueWithShadow<u16>(cx().value() - 1, cx().shadow()));
return cx().value() == 0;
default:
VERIFY_NOT_REACHED();
}
VERIFY_NOT_REACHED();
}
ALWAYS_INLINE void step_source_index(X86::AddressSize address_size, u32 step)