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https://github.com/RGBCube/serenity
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UserspaceEmulator: Sketch out a SoftFPU interface
This commit is contained in:
Hendiadyoin1
Andreas Kling
parent
1d74742c29
commit
09a1a0b319
2 changed files with 860 additions and 0 deletions
248
Userland/DevTools/UserspaceEmulator/SoftFPU.cpp
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248
Userland/DevTools/UserspaceEmulator/SoftFPU.cpp
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/*
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* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
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* Copyright (c) 2021, Leon Albrecht <leon2002.la@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include "SoftFPU.h"
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#include "Emulator.h"
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#include "SoftCPU.h"
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#include "ValueWithShadow.h"
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#include <AK/BitCast.h>
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#include <AK/NumericLimits.h>
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#include <AK/UFixedBigInt.h>
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#include <unistd.h>
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#if defined(__GNUC__) && !defined(__clang__)
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# pragma GCC optimize("O3")
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#endif
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#define TODO_INSN() \
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do { \
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reportln("\n=={}== Unimplemented instruction: {}\n", getpid(), __FUNCTION__); \
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m_emulator.dump_backtrace(); \
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_exit(0); \
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} while (0)
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template<typename T>
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ALWAYS_INLINE void warn_if_uninitialized(T value_with_shadow, const char* message)
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{
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if (value_with_shadow.is_uninitialized()) [[unlikely]] {
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reportln("\033[31;1mWarning! Use of uninitialized value: {}\033[0m\n", message);
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UserspaceEmulator::Emulator::the().dump_backtrace();
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}
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}
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namespace UserspaceEmulator {
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ALWAYS_INLINE void SoftFPU::warn_if_fpu_not_set_absolute(u8 index) const
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{
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if (!fpu_is_set(index)) [[unlikely]] {
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// FIXME: Are we supposed to set a flag here?
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// We might need to raise a stack underflow here
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reportln("\033[31;1mWarning! Read of uninitialized value on the FPU Stack ({} abs)\033[0m\n", index);
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m_emulator.dump_backtrace();
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}
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}
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ALWAYS_INLINE void SoftFPU::warn_if_mmx_absolute(u8 index) const
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{
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if (m_reg_is_mmx[index]) [[unlikely]] {
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reportln("\033[31;1mWarning! Use of an MMX register as an FPU value ({} abs)\033[0m\n", index);
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m_emulator.dump_backtrace();
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}
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}
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ALWAYS_INLINE void SoftFPU::warn_if_fpu_absolute(u8 index) const
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{
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if (!m_reg_is_mmx[index]) [[unlikely]] {
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reportln("\033[31;1mWarning! Use of an FPU value ({} abs) as an MMX register\033[0m\n", index);
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m_emulator.dump_backtrace();
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}
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}
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ALWAYS_INLINE long double SoftFPU::fpu_get(u8 index) const
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{
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VERIFY(index < 8);
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warn_if_fpu_not_set_absolute(index);
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warn_if_mmx_absolute(index);
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u8 effective_index = (m_fpu_stack_top + index) % 8;
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return m_storage[effective_index].fp;
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}
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ALWAYS_INLINE void SoftFPU::fpu_set_absolute(u8 index, long double value)
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{
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VERIFY(index < 8);
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set_tag_from_value_absolute(index, value);
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m_storage[index].fp = value;
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m_reg_is_mmx[index] = false;
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}
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ALWAYS_INLINE void SoftFPU::fpu_set(u8 index, long double value)
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{
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VERIFY(index < 8);
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fpu_set_absolute((m_fpu_stack_top + index) % 8, value);
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}
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ALWAYS_INLINE MMX SoftFPU::mmx_get(u8 index) const
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{
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VERIFY(index < 8);
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warn_if_fpu_absolute(index);
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return m_storage[index].mmx;
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}
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ALWAYS_INLINE void SoftFPU::mmx_set(u8 index, MMX value)
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{
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m_storage[index].mmx = value;
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// The high bytes are set to 0b11... to make the floatingpoint value NaN.
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// This way we are technically able to find out if we are reading the wrong
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// type, but this is still difficult, so we use our own lookup for that
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// We set the alignment bytes to all 1's, too, just in case
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m_storage[index].__high = ~(decltype(m_storage[index].__high))0u;
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m_reg_is_mmx[index] = true;
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}
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ALWAYS_INLINE void SoftFPU::fpu_push(long double value)
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{
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if (fpu_is_set(7))
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fpu_set_stack_overflow();
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m_fpu_stack_top = (m_fpu_stack_top - 1u) % 8;
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fpu_set(0, value);
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}
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ALWAYS_INLINE long double SoftFPU::fpu_pop()
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{
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warn_if_mmx_absolute(m_fpu_stack_top);
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if (!fpu_is_set(0))
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fpu_set_stack_underflow();
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auto ret = fpu_get(0);
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fpu_set_tag(0, FPU_Tag::Empty);
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m_fpu_stack_top = (m_fpu_stack_top + 1u) % 8;
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return ret;
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}
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ALWAYS_INLINE void SoftFPU::fpu_set_exception(FPU_Exception ex)
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{
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switch (ex) {
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case FPU_Exception::StackFault:
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m_fpu_error_stackfault = 1;
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m_fpu_error_invalid = 1; // Implies InvalidOperation
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break;
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case FPU_Exception::InvalidOperation:
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m_fpu_error_invalid = 1;
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if (!m_fpu_mask_invalid)
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break;
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return;
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case FPU_Exception::DenormalizedOperand:
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m_fpu_error_denorm = 1;
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if (!m_fpu_mask_denorm)
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break;
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return;
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case FPU_Exception::ZeroDivide:
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m_fpu_error_zero_div = 1;
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if (!m_fpu_mask_zero_div)
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break;
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return;
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case FPU_Exception::Overflow:
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m_fpu_error_overflow = 1;
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if (!m_fpu_mask_overflow)
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break;
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return;
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case FPU_Exception::Underflow:
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m_fpu_error_underflow = 1;
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if (!m_fpu_mask_underflow)
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break;
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return;
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case FPU_Exception::Precision:
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m_fpu_error_precision = 1;
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if (!m_fpu_mask_precision)
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break;
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return;
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}
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// set exception bit
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m_fpu_error_summary = 1;
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// FIXME: set traceback
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// For that we need to get the currently executing instruction and
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// the previous eip
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// FIXME: Call FPU Exception handler
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reportln("Trying to call Exception handler from {}", fpu_exception_string(ex));
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fpu_dump_env();
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m_emulator.dump_backtrace();
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TODO();
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}
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template<Arithmetic T>
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__attribute__((pure)) ALWAYS_INLINE T SoftFPU::fpu_round(long double value) const
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{
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// FIXME: may need to set indefinite values manually
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switch (fpu_get_round_mode()) {
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case RoundingMode::NEAREST:
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return static_cast<T>(roundl(value));
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case RoundingMode::DOWN:
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return static_cast<T>(floorl(value));
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case RoundingMode::UP:
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return static_cast<T>(ceill(value));
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case RoundingMode::TRUNK:
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return static_cast<T>(truncl(value));
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default:
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VERIFY_NOT_REACHED();
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}
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}
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template<Arithmetic T>
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__attribute__((pure)) ALWAYS_INLINE T SoftFPU::fpu_round_checked(long double value)
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{
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T result = fpu_round<T>(value);
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if (auto rnd = value - result) {
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if (rnd > 0)
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set_c1(1);
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else
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set_c1(0);
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fpu_set_exception(FPU_Exception::Precision);
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}
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return result;
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}
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template<FloatingPoint T>
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__attribute__((pure)) ALWAYS_INLINE T SoftFPU::fpu_convert(long double value) const
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{
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// FIXME: actually round the right way
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return static_cast<T>(value);
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}
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template<FloatingPoint T>
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__attribute__((pure)) ALWAYS_INLINE T SoftFPU::fpu_convert_checked(long double value)
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{
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T result = fpu_convert<T>(value);
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if (auto rnd = value - result) {
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if (rnd > 0)
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set_c1(1);
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else
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set_c1(0);
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fpu_set_exception(FPU_Exception::Precision);
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}
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return result;
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}
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template<Signed R, Signed I>
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__attribute__((const)) ALWAYS_INLINE R signed_saturate(I input)
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{
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if (input > NumericLimits<R>::max())
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return NumericLimits<R>::max();
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if (input < NumericLimits<R>::min())
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return NumericLimits<R>::min();
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return static_cast<R>(input);
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}
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template<Unsigned R, Unsigned I>
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__attribute__((const)) ALWAYS_INLINE R unsigned_saturate(I input)
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{
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if (input > NumericLimits<R>::max())
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return NumericLimits<R>::max();
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return static_cast<R>(input);
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}
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}
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612
Userland/DevTools/UserspaceEmulator/SoftFPU.h
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612
Userland/DevTools/UserspaceEmulator/SoftFPU.h
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@ -0,0 +1,612 @@
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/*
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* Copyright (c) 2021, Leon Albrecht <leon2002.la@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include "Report.h"
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#include <AK/Concepts.h>
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#include <AK/SIMD.h>
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#include <LibX86/Instruction.h>
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#include <LibX86/Interpreter.h>
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#include <math.h>
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#include <string.h>
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namespace UserspaceEmulator {
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using namespace AK::SIMD;
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class Emulator;
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class SoftCPU;
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union MMX {
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u64 raw;
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c8x8 v8;
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i16x4 v16;
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i32x2 v32;
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i16x4 v16u;
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i32x2 v32u;
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};
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static_assert(sizeof(MMX) == sizeof(u64));
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class SoftFPU final {
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public:
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SoftFPU(Emulator& emulator, SoftCPU& cpu)
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: m_emulator(emulator)
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, m_cpu(cpu)
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{
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}
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ALWAYS_INLINE bool c0() const { return m_fpu_c0; }
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ALWAYS_INLINE bool c1() const { return m_fpu_c1; }
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ALWAYS_INLINE bool c2() const { return m_fpu_c2; }
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ALWAYS_INLINE bool c3() const { return m_fpu_c3; }
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ALWAYS_INLINE void set_c0(bool val) { m_fpu_c0 = val; }
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ALWAYS_INLINE void set_c1(bool val) { m_fpu_c1 = val; }
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ALWAYS_INLINE void set_c2(bool val) { m_fpu_c2 = val; }
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ALWAYS_INLINE void set_c3(bool val) { m_fpu_c3 = val; }
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long double fpu_get(u8 index) const;
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void fpu_push(long double value);
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long double fpu_pop();
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void fpu_set_absolute(u8 index, long double value);
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void fpu_set(u8 index, long double value);
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MMX mmx_get(u8 index) const;
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void mmx_set(u8 index, MMX value);
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private:
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friend class SoftCPU;
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Emulator& m_emulator;
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SoftCPU& m_cpu;
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enum class FPU_Exception : u8 {
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InvalidOperation,
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DenormalizedOperand,
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ZeroDivide,
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Overflow,
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Underflow,
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Precision,
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StackFault,
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};
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enum class FPU_Tag : u8 {
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Valid = 0b00,
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Zero = 0b01,
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Special = 0b10,
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Empty = 0b11
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};
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enum class RoundingMode : u8 {
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NEAREST = 0b00,
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DOWN = 0b01,
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UP = 0b10,
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TRUNK = 0b11
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};
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void fpu_dump_env()
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{
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reportln("Exceptions: #I:{} #D:{} #O:{} #D:{} #U:{} #P:{} #SF:{} Summary:{}",
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m_fpu_error_invalid,
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m_fpu_error_denorm,
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m_fpu_error_zero_div,
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m_fpu_error_overflow,
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m_fpu_error_underflow,
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m_fpu_error_precision,
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m_fpu_error_stackfault,
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m_fpu_error_summary);
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reportln("Masks: #I:{} #D:{} #O:{} #D:{} #U:{} #P:{}",
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m_fpu_mask_invalid,
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m_fpu_mask_denorm,
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m_fpu_mask_zero_div,
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m_fpu_mask_overflow,
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m_fpu_mask_underflow,
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m_fpu_mask_precision);
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reportln("C0:{} C1:{} C2:{} C3:{}", c0(), c1(), c2(), c3());
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reportln("fpu-stacktop: {}", m_fpu_stack_top);
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reportln("fpu-stack /w stacktop (real):");
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for (u8 i = 0; i < 8; ++i) {
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reportln("\t{} ({}): fp {} ({}), mmx (:x016)", i, (u8)((m_fpu_stack_top + i) % 8), m_storage[(m_fpu_stack_top + i) % 8].fp, fpu_is_set(i) ? "set" : "free", m_storage[(m_fpu_stack_top + i) % 8].mmx.raw);
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}
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}
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String fpu_exception_string(FPU_Exception ex)
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{
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switch (ex) {
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case FPU_Exception::StackFault:
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return "Stackfault";
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case FPU_Exception::InvalidOperation:
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return "Invalid Operation";
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case FPU_Exception::DenormalizedOperand:
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return "Denormalized Operant";
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case FPU_Exception::ZeroDivide:
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return "Divide by Zero";
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case FPU_Exception::Overflow:
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return "Overflow";
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case FPU_Exception::Underflow:
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return "Underflow";
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case FPU_Exception::Precision:
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return "Precision";
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}
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VERIFY_NOT_REACHED();
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}
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// FIXME: Technically we should check for exceptions after each insn, too,
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// this might be important for FLDENV, but otherwise it should
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// be fine this way
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void fpu_set_exception(FPU_Exception ex);
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ALWAYS_INLINE void fpu_set_stack_overflow()
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{
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reportln("Stack Overflow");
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set_c1(1);
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fpu_set_exception(FPU_Exception::StackFault);
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}
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ALWAYS_INLINE void fpu_set_stack_underflow()
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{
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reportln("Stack Underflow");
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set_c1(0);
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fpu_set_exception(FPU_Exception::StackFault);
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}
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constexpr FPU_Tag fpu_get_tag_absolute(u8 index) const
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{
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switch (index) {
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case 0:
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return FPU_Tag(m_fpu_status_0);
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case 1:
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return FPU_Tag(m_fpu_status_1);
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case 2:
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return FPU_Tag(m_fpu_status_2);
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case 3:
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return FPU_Tag(m_fpu_status_3);
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case 4:
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return FPU_Tag(m_fpu_status_4);
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case 5:
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return FPU_Tag(m_fpu_status_5);
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case 6:
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return FPU_Tag(m_fpu_status_6);
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case 7:
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return FPU_Tag(m_fpu_status_7);
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default:
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VERIFY_NOT_REACHED();
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}
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}
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constexpr FPU_Tag fpu_get_tag(u8 index) const
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{
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VERIFY(index < 8);
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return fpu_get_tag_absolute((m_fpu_stack_top + index) % 8);
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}
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ALWAYS_INLINE void fpu_set_tag_absolute(u8 index, FPU_Tag tag)
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{
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switch (index) {
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case 0:
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m_fpu_status_0 = (u8)tag;
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break;
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case 1:
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m_fpu_status_1 = (u8)tag;
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break;
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case 2:
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m_fpu_status_2 = (u8)tag;
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break;
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case 3:
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m_fpu_status_3 = (u8)tag;
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break;
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case 4:
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m_fpu_status_4 = (u8)tag;
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break;
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case 5:
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m_fpu_status_5 = (u8)tag;
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break;
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case 6:
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m_fpu_status_6 = (u8)tag;
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break;
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case 7:
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m_fpu_status_7 = (u8)tag;
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break;
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default:
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
}
|
||||
|
||||
ALWAYS_INLINE void fpu_set_tag(u8 index, FPU_Tag tag)
|
||||
{
|
||||
VERIFY(index < 8);
|
||||
fpu_set_tag_absolute((m_fpu_stack_top + index) % 8, tag);
|
||||
}
|
||||
|
||||
ALWAYS_INLINE void set_tag_from_value_absolute(u8 index, long double val)
|
||||
{
|
||||
switch (fpclassify(val)) {
|
||||
case FP_ZERO:
|
||||
fpu_set_tag_absolute(index, FPU_Tag::Zero);
|
||||
break;
|
||||
case FP_NAN:
|
||||
case FP_INFINITE:
|
||||
case FP_SUBNORMAL:
|
||||
fpu_set_tag_absolute(index, FPU_Tag::Special);
|
||||
break;
|
||||
case FP_NORMAL:
|
||||
fpu_set_tag_absolute(index, FPU_Tag::Valid);
|
||||
break;
|
||||
default:
|
||||
VERIFY_NOT_REACHED();
|
||||
}
|
||||
}
|
||||
|
||||
ALWAYS_INLINE void set_tag_from_value(u8 index, long double val)
|
||||
{
|
||||
set_tag_from_value_absolute((m_fpu_stack_top + index) % 8, val);
|
||||
}
|
||||
|
||||
ALWAYS_INLINE bool fpu_isnan(u8 index) const
|
||||
{
|
||||
return isnan(fpu_get(index));
|
||||
}
|
||||
|
||||
ALWAYS_INLINE bool fpu_is_set(u8 index) const
|
||||
{
|
||||
return fpu_get_tag_absolute((m_fpu_stack_top + index) % 8) != FPU_Tag::Empty;
|
||||
}
|
||||
|
||||
ALWAYS_INLINE RoundingMode fpu_get_round_mode() const
|
||||
{
|
||||
return RoundingMode(m_fpu_round_mode);
|
||||
}
|
||||
|
||||
template<Arithmetic T>
|
||||
T fpu_round(long double) const;
|
||||
template<Arithmetic T>
|
||||
T fpu_round_checked(long double);
|
||||
|
||||
template<FloatingPoint T>
|
||||
T fpu_convert(long double) const;
|
||||
template<FloatingPoint T>
|
||||
T fpu_convert_checked(long double);
|
||||
|
||||
ALWAYS_INLINE void fpu_set_unordered()
|
||||
{
|
||||
set_c0(1);
|
||||
set_c2(1);
|
||||
set_c3(1);
|
||||
}
|
||||
void warn_if_mmx_absolute(u8 index) const;
|
||||
void warn_if_fpu_absolute(u8 index) const;
|
||||
void warn_if_fpu_not_set_absolute(u8 index) const;
|
||||
|
||||
void mmx_common() { m_fpu_tw = 0; }
|
||||
|
||||
bool m_reg_is_mmx[8] { false };
|
||||
|
||||
union {
|
||||
long double fp;
|
||||
struct {
|
||||
MMX mmx;
|
||||
Conditional<sizeof(long double) == 16,
|
||||
u64,
|
||||
Conditional<sizeof(long double) == 12,
|
||||
u32,
|
||||
u16>>
|
||||
__high;
|
||||
};
|
||||
} m_storage[8];
|
||||
|
||||
union {
|
||||
u16 m_fpu_cw { 0x037F };
|
||||
struct {
|
||||
u16 m_fpu_mask_invalid : 1;
|
||||
u16 m_fpu_mask_denorm : 1;
|
||||
u16 m_fpu_mask_zero_div : 1;
|
||||
u16 m_fpu_mask_overflow : 1;
|
||||
u16 m_fpu_mask_underflow : 1;
|
||||
u16 m_fpu_mask_precision : 1;
|
||||
u16 : 2; // unused
|
||||
u16 m_fpu_precission : 2;
|
||||
u16 m_fpu_round_mode : 2;
|
||||
u16 m_fpu_infinity_control : 1;
|
||||
u16 : 3; // unused
|
||||
};
|
||||
};
|
||||
|
||||
union {
|
||||
u16 m_fpu_sw { 0 };
|
||||
struct {
|
||||
u16 m_fpu_error_invalid : 1; // pre | IE -> #I (#IS, #IA)
|
||||
u16 m_fpu_error_denorm : 1; // pre | DE -> #D
|
||||
u16 m_fpu_error_zero_div : 1; // pre | ZE -> #Z
|
||||
u16 m_fpu_error_overflow : 1; // post| OE -> #O
|
||||
u16 m_fpu_error_underflow : 1; // post| UE -> #U
|
||||
u16 m_fpu_error_precision : 1; // post| PE -> #P
|
||||
u16 m_fpu_error_stackfault : 1; // SF
|
||||
u16 m_fpu_error_summary : 1;
|
||||
u16 m_fpu_c0 : 1;
|
||||
u16 m_fpu_c1 : 1;
|
||||
u16 m_fpu_c2 : 1;
|
||||
u16 m_fpu_stack_top : 3;
|
||||
u16 m_fpu_c3 : 1;
|
||||
u16 m_fpu_busy : 1;
|
||||
};
|
||||
};
|
||||
|
||||
union {
|
||||
u16 m_fpu_tw { 0xFFFF };
|
||||
struct {
|
||||
u16 m_fpu_status_0 : 2;
|
||||
u16 m_fpu_status_1 : 2;
|
||||
u16 m_fpu_status_2 : 2;
|
||||
u16 m_fpu_status_3 : 2;
|
||||
u16 m_fpu_status_4 : 2;
|
||||
u16 m_fpu_status_5 : 2;
|
||||
u16 m_fpu_status_6 : 2;
|
||||
u16 m_fpu_status_7 : 2;
|
||||
};
|
||||
};
|
||||
|
||||
u32 m_fpu_ip { 0 };
|
||||
u16 m_fpu_cs { 0 };
|
||||
|
||||
u32 m_fpu_dp { 0 };
|
||||
u16 m_fpu_ds { 0 };
|
||||
|
||||
u16 m_fpu_iop { 0 };
|
||||
|
||||
// Instructions
|
||||
|
||||
// DATA TRANSFER
|
||||
void FLD_RM32(const X86::Instruction&);
|
||||
void FLD_RM64(const X86::Instruction&);
|
||||
void FLD_RM80(const X86::Instruction&);
|
||||
|
||||
void FST_RM32(const X86::Instruction&);
|
||||
void FST_RM64(const X86::Instruction&);
|
||||
void FSTP_RM32(const X86::Instruction&);
|
||||
void FSTP_RM64(const X86::Instruction&);
|
||||
void FSTP_RM80(const X86::Instruction&);
|
||||
|
||||
void FILD_RM32(const X86::Instruction&);
|
||||
void FILD_RM16(const X86::Instruction&);
|
||||
void FILD_RM64(const X86::Instruction&);
|
||||
|
||||
void FIST_RM16(const X86::Instruction&);
|
||||
void FIST_RM32(const X86::Instruction&);
|
||||
void FISTP_RM16(const X86::Instruction&);
|
||||
void FISTP_RM32(const X86::Instruction&);
|
||||
void FISTP_RM64(const X86::Instruction&);
|
||||
void FISTTP_RM16(const X86::Instruction&);
|
||||
void FISTTP_RM32(const X86::Instruction&);
|
||||
void FISTTP_RM64(const X86::Instruction&);
|
||||
|
||||
void FBLD_M80(const X86::Instruction&);
|
||||
void FBSTP_M80(const X86::Instruction&);
|
||||
|
||||
void FXCH(const X86::Instruction&);
|
||||
|
||||
void FCMOVE(const X86::Instruction&);
|
||||
void FCMOVNE(const X86::Instruction&);
|
||||
void FCMOVB(const X86::Instruction&);
|
||||
void FCMOVBE(const X86::Instruction&);
|
||||
void FCMOVNB(const X86::Instruction&);
|
||||
void FCMOVNBE(const X86::Instruction&);
|
||||
void FCMOVU(const X86::Instruction&);
|
||||
void FCMOVNU(const X86::Instruction&);
|
||||
|
||||
// BASIC ARITHMETIC
|
||||
void FADD_RM32(const X86::Instruction&);
|
||||
void FADD_RM64(const X86::Instruction&);
|
||||
void FADDP(const X86::Instruction&);
|
||||
|
||||
void FIADD_RM16(const X86::Instruction&);
|
||||
void FIADD_RM32(const X86::Instruction&);
|
||||
|
||||
void FSUB_RM32(const X86::Instruction&);
|
||||
void FSUB_RM64(const X86::Instruction&);
|
||||
void FSUBP(const X86::Instruction&);
|
||||
void FSUBR_RM32(const X86::Instruction&);
|
||||
void FSUBR_RM64(const X86::Instruction&);
|
||||
void FSUBRP(const X86::Instruction&);
|
||||
|
||||
void FISUB_RM16(const X86::Instruction&);
|
||||
void FISUB_RM32(const X86::Instruction&);
|
||||
void FISUBR_RM16(const X86::Instruction&);
|
||||
void FISUBR_RM32(const X86::Instruction&);
|
||||
|
||||
void FMUL_RM32(const X86::Instruction&);
|
||||
void FMUL_RM64(const X86::Instruction&);
|
||||
void FMULP(const X86::Instruction&);
|
||||
|
||||
void FIMUL_RM16(const X86::Instruction&);
|
||||
void FIMUL_RM32(const X86::Instruction&);
|
||||
|
||||
void FDIV_RM32(const X86::Instruction&);
|
||||
void FDIV_RM64(const X86::Instruction&);
|
||||
void FDIVP(const X86::Instruction&);
|
||||
void FDIVR_RM32(const X86::Instruction&);
|
||||
void FDIVR_RM64(const X86::Instruction&);
|
||||
void FDIVRP(const X86::Instruction&);
|
||||
|
||||
void FIDIV_RM16(const X86::Instruction&);
|
||||
void FIDIV_RM32(const X86::Instruction&);
|
||||
void FIDIVR_RM16(const X86::Instruction&);
|
||||
void FIDIVR_RM32(const X86::Instruction&);
|
||||
|
||||
void FPREM(const X86::Instruction&);
|
||||
void FPREM1(const X86::Instruction&);
|
||||
|
||||
void FABS(const X86::Instruction&);
|
||||
void FCHS(const X86::Instruction&);
|
||||
|
||||
void FRNDINT(const X86::Instruction&);
|
||||
|
||||
void FSCALE(const X86::Instruction&);
|
||||
|
||||
void FSQRT(const X86::Instruction&);
|
||||
|
||||
void FXTRACT(const X86::Instruction&);
|
||||
|
||||
// COMPARISON
|
||||
void FCOM_RM32(const X86::Instruction&);
|
||||
void FCOM_RM64(const X86::Instruction&);
|
||||
void FCOMP_RM32(const X86::Instruction&);
|
||||
void FCOMP_RM64(const X86::Instruction&);
|
||||
void FCOMPP(const X86::Instruction&);
|
||||
void FCOMI(const X86::Instruction&);
|
||||
void FCOMIP(const X86::Instruction&);
|
||||
|
||||
void FUCOM(const X86::Instruction&);
|
||||
void FUCOMP(const X86::Instruction&);
|
||||
void FUCOMPP(const X86::Instruction&);
|
||||
void FUCOMI(const X86::Instruction&);
|
||||
void FUCOMIP(const X86::Instruction&);
|
||||
|
||||
void FICOM_RM16(const X86::Instruction&);
|
||||
void FICOM_RM32(const X86::Instruction&);
|
||||
void FICOMP_RM16(const X86::Instruction&);
|
||||
void FICOMP_RM32(const X86::Instruction&);
|
||||
|
||||
void FTST(const X86::Instruction&);
|
||||
void FXAM(const X86::Instruction&);
|
||||
|
||||
// TRANSCENDENTAL
|
||||
void FSIN(const X86::Instruction&);
|
||||
void FCOS(const X86::Instruction&);
|
||||
void FSINCOS(const X86::Instruction&);
|
||||
void FPTAN(const X86::Instruction&);
|
||||
void FPATAN(const X86::Instruction&);
|
||||
|
||||
void F2XM1(const X86::Instruction&);
|
||||
void FYL2X(const X86::Instruction&);
|
||||
void FYL2XP1(const X86::Instruction&);
|
||||
|
||||
// CONSTANT LOAD
|
||||
void FLD1(const X86::Instruction&);
|
||||
void FLDZ(const X86::Instruction&);
|
||||
void FLDPI(const X86::Instruction&);
|
||||
void FLDL2E(const X86::Instruction&);
|
||||
void FLDLN2(const X86::Instruction&);
|
||||
void FLDL2T(const X86::Instruction&);
|
||||
void FLDLG2(const X86::Instruction&);
|
||||
|
||||
// CONTROL
|
||||
void FINCSTP(const X86::Instruction&);
|
||||
void FDECSTP(const X86::Instruction&);
|
||||
void FFREE(const X86::Instruction&);
|
||||
void FFREEP(const X86::Instruction&); // undocumented
|
||||
|
||||
// FIXME: Non N- versions?
|
||||
void FNINIT(const X86::Instruction&);
|
||||
void FNCLEX(const X86::Instruction&);
|
||||
|
||||
void FNSTCW(const X86::Instruction&);
|
||||
void FLDCW(const X86::Instruction&);
|
||||
|
||||
void FNSTENV(const X86::Instruction&);
|
||||
void FLDENV(const X86::Instruction&);
|
||||
|
||||
void FNSAVE(const X86::Instruction&);
|
||||
void FRSTOR(const X86::Instruction&);
|
||||
|
||||
void FNSTSW(const X86::Instruction&);
|
||||
void FNSTSW_AX(const X86::Instruction&);
|
||||
|
||||
// FIXME: WAIT && FWAIT
|
||||
void FNOP(const X86::Instruction&);
|
||||
|
||||
// FPU & SIMD MANAGEMENT
|
||||
// FIXME: FXSAVE && FXRSTOR
|
||||
|
||||
// DO NOTHING?
|
||||
// FIXME: FENI, FDISI, FSETPM
|
||||
void FNENI(const X86::Instruction&);
|
||||
void FNDISI(const X86::Instruction&);
|
||||
void FNSETPM(const X86::Instruction&);
|
||||
|
||||
// MMX
|
||||
// ARITHMETIC
|
||||
void PADDB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PADDW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PADDD_mm1_mm2m64(const X86::Instruction&);
|
||||
void PADDSB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PADDSW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PADDUSB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PADDUSW_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
void PSUBB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSUBW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSUBD_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSUBSB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSUBSW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSUBUSB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSUBUSW_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
void PMULHW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PMULLW_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
void PMADDWD_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
// COMPARISON
|
||||
void PCMPEQB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PCMPEQW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PCMPEQD_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
void PCMPGTB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PCMPGTW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PCMPGTD_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
// CONVERSION
|
||||
void PACKSSDW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PACKSSWB_mm1_mm2m64(const X86::Instruction&);
|
||||
void PACKUSWB_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
// UNPACK
|
||||
void PUNPCKHBW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PUNPCKHWD_mm1_mm2m64(const X86::Instruction&);
|
||||
void PUNPCKHDQ_mm1_mm2m64(const X86::Instruction&);
|
||||
void PUNPCKLBW_mm1_mm2m32(const X86::Instruction&);
|
||||
void PUNPCKLWD_mm1_mm2m32(const X86::Instruction&);
|
||||
void PUNPCKLDQ_mm1_mm2m32(const X86::Instruction&);
|
||||
|
||||
// LOGICAL
|
||||
void PAND_mm1_mm2m64(const X86::Instruction&);
|
||||
void PANDN_mm1_mm2m64(const X86::Instruction&);
|
||||
void POR_mm1_mm2m64(const X86::Instruction&);
|
||||
void PXOR_mm1_mm2m64(const X86::Instruction&);
|
||||
|
||||
// SHIFT
|
||||
void PSLLW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSLLW_mm1_imm8(const X86::Instruction&);
|
||||
void PSLLD_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSLLD_mm1_imm8(const X86::Instruction&);
|
||||
void PSLLQ_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSLLQ_mm1_imm8(const X86::Instruction&);
|
||||
void PSRAW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSRAW_mm1_imm8(const X86::Instruction&);
|
||||
void PSRAD_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSRAD_mm1_imm8(const X86::Instruction&);
|
||||
void PSRLW_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSRLW_mm1_imm8(const X86::Instruction&);
|
||||
void PSRLD_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSRLD_mm1_imm8(const X86::Instruction&);
|
||||
void PSRLQ_mm1_mm2m64(const X86::Instruction&);
|
||||
void PSRLQ_mm1_imm8(const X86::Instruction&);
|
||||
|
||||
// DATA TRANSFER
|
||||
void MOVD_mm1_rm32(const X86::Instruction&);
|
||||
void MOVD_rm32_mm2(const X86::Instruction&);
|
||||
|
||||
void MOVQ_mm1_mm2m64(const X86::Instruction&);
|
||||
void MOVQ_mm1m64_mm2(const X86::Instruction&);
|
||||
void MOVQ_mm1_rm64(const X86::Instruction&); // long mode
|
||||
void MOVQ_rm64_mm2(const X86::Instruction&); // long mode
|
||||
|
||||
// EMPTY MMX STATE
|
||||
void EMMS(const X86::Instruction&);
|
||||
};
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue