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https://github.com/RGBCube/serenity
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UserspaceEmulator+LibX86: Implement all the forms of XOR
And they're all generic, which will make it easy to support more ops.
This commit is contained in:
Andreas Kling
parent
9955819d92
commit
0cf7fd5268
3 changed files with 204 additions and 38 deletions
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@ -149,12 +149,57 @@ static typename TypeDoubler<Destination>::type op_xor(SoftCPU& cpu, Destination&
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}
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template<typename Op>
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void SoftCPU::generic_RM32_reg32(Op op, const X86::Instruction& insn)
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void SoftCPU::generic_AL_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read32(*this, insn);
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auto src = gpr32(insn.reg32());
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auto dest = al();
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auto src = insn.imm8();
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auto result = op(*this, dest, src);
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insn.modrm().write32(*this, insn, result);
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set_al(result);
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}
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template<typename Op>
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void SoftCPU::generic_AX_imm16(Op op, const X86::Instruction& insn)
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{
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auto dest = ax();
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auto src = insn.imm16();
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auto result = op(*this, dest, src);
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set_ax(result);
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}
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template<typename Op>
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void SoftCPU::generic_EAX_imm32(Op op, const X86::Instruction& insn)
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{
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auto dest = eax();
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auto src = insn.imm32();
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auto result = op(*this, dest, src);
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set_eax(result);
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}
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template<typename Op>
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void SoftCPU::generic_RM16_imm16(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read16(*this, insn);
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auto src = insn.imm16();
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auto result = op(*this, dest, src);
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insn.modrm().write16(*this, insn, result);
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}
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template<typename Op>
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void SoftCPU::generic_RM16_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read16(*this, insn);
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auto src = insn.imm8();
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auto result = op(*this, dest, src);
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insn.modrm().write16(*this, insn, result);
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}
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template<typename Op>
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void SoftCPU::generic_RM16_reg16(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read16(*this, insn);
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auto src = gpr16(insn.reg16());
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auto result = op(*this, dest, src);
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insn.modrm().write16(*this, insn, result);
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}
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template<typename Op>
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@ -175,6 +220,60 @@ void SoftCPU::generic_RM32_imm8(Op op, const X86::Instruction& insn)
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insn.modrm().write32(*this, insn, result);
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}
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template<typename Op>
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void SoftCPU::generic_RM32_reg32(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read32(*this, insn);
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auto src = gpr32(insn.reg32());
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auto result = op(*this, dest, src);
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insn.modrm().write32(*this, insn, result);
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}
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template<typename Op>
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void SoftCPU::generic_RM8_imm8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read8(*this, insn);
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auto src = insn.imm8();
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auto result = op(*this, dest, src);
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insn.modrm().write8(*this, insn, result);
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}
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template<typename Op>
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void SoftCPU::generic_RM8_reg8(Op op, const X86::Instruction& insn)
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{
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auto dest = insn.modrm().read8(*this, insn);
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auto src = gpr8(insn.reg8());
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auto result = op(*this, dest, src);
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insn.modrm().write8(*this, insn, result);
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}
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template<typename Op>
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void SoftCPU::generic_reg16_RM16(Op op, const X86::Instruction& insn)
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{
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auto dest = gpr16(insn.reg16());
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auto src = insn.modrm().read16(*this, insn);
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auto result = op(*this, dest, src);
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gpr16(insn.reg16()) = result;
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}
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template<typename Op>
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void SoftCPU::generic_reg32_RM32(Op op, const X86::Instruction& insn)
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{
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auto dest = gpr32(insn.reg32());
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auto src = insn.modrm().read32(*this, insn);
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auto result = op(*this, dest, src);
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gpr32(insn.reg32()) = result;
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}
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template<typename Op>
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void SoftCPU::generic_reg8_RM8(Op op, const X86::Instruction& insn)
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{
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auto dest = gpr8(insn.reg8());
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auto src = insn.modrm().read8(*this, insn);
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auto result = op(*this, dest, src);
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gpr8(insn.reg8()) = result;
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}
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void SoftCPU::AAA(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAD(const X86::Instruction&) { TODO(); }
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void SoftCPU::AAM(const X86::Instruction&) { TODO(); }
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@ -646,38 +745,24 @@ void SoftCPU::XCHG_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::XCHG_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::XLAT(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_AL_imm8(const X86::Instruction&)
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{
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#define DEFINE_GENERIC_INSN_HANDLERS(mnemonic, op) \
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void SoftCPU::mnemonic##_AL_imm8(const X86::Instruction& insn) { generic_AL_imm8(op<u8, u8>, insn); } \
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void SoftCPU::mnemonic##_AX_imm16(const X86::Instruction& insn) { generic_AX_imm16(op<u16, u16>, insn); } \
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void SoftCPU::mnemonic##_EAX_imm32(const X86::Instruction& insn) { generic_EAX_imm32(op<u32, u32>, insn); } \
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void SoftCPU::mnemonic##_RM16_imm16(const X86::Instruction& insn) { generic_RM16_imm16(op<u16, u16>, insn); } \
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void SoftCPU::mnemonic##_RM16_imm8(const X86::Instruction& insn) { generic_RM16_imm8(op<u16, u8>, insn); } \
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void SoftCPU::mnemonic##_RM16_reg16(const X86::Instruction& insn) { generic_RM16_reg16(op<u16, u16>, insn); } \
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void SoftCPU::mnemonic##_RM32_imm32(const X86::Instruction& insn) { generic_RM32_imm32(op<u32, u32>, insn); } \
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void SoftCPU::mnemonic##_RM32_imm8(const X86::Instruction& insn) { generic_RM32_imm8(op<u32, u8>, insn); } \
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void SoftCPU::mnemonic##_RM32_reg32(const X86::Instruction& insn) { generic_RM32_reg32(op<u32, u32>, insn); } \
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void SoftCPU::mnemonic##_RM8_imm8(const X86::Instruction& insn) { generic_RM8_imm8(op<u8, u8>, insn); } \
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void SoftCPU::mnemonic##_RM8_reg8(const X86::Instruction& insn) { generic_RM8_reg8(op<u8, u8>, insn); } \
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void SoftCPU::mnemonic##_reg16_RM16(const X86::Instruction& insn) { generic_reg16_RM16(op<u16, u16>, insn); } \
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void SoftCPU::mnemonic##_reg32_RM32(const X86::Instruction& insn) { generic_reg32_RM32(op<u32, u32>, insn); } \
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void SoftCPU::mnemonic##_reg8_RM8(const X86::Instruction& insn) { generic_reg8_RM8(op<u8, u8>, insn); }
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TODO();
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}
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DEFINE_GENERIC_INSN_HANDLERS(XOR, op_xor)
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void SoftCPU::XOR_AX_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_EAX_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_RM16_imm16(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_RM16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_RM16_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_RM32_imm32(const X86::Instruction& insn)
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{
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generic_RM32_imm32(op_xor<u32, u32>, insn);
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}
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void SoftCPU::XOR_RM32_imm8(const X86::Instruction& insn)
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{
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generic_RM32_imm8(op_xor<u32, u8>, insn);
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}
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void SoftCPU::XOR_RM32_reg32(const X86::Instruction& insn)
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{
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generic_RM32_reg32(op_xor<u32, u32>, insn);
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}
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void SoftCPU::XOR_RM8_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_RM8_reg8(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_reg16_RM16(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_reg8_RM8(const X86::Instruction&) { TODO(); }
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void SoftCPU::MOVQ_mm1_mm2m64(const X86::Instruction&) { TODO(); }
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void SoftCPU::EMMS(const X86::Instruction&) { TODO(); }
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void SoftCPU::MOVQ_mm1_m64_mm2(const X86::Instruction&) { TODO(); }
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@ -690,5 +775,4 @@ void SoftCPU::wrap_0xD1_32(const X86::Instruction&) { TODO(); }
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void SoftCPU::wrap_0xD2(const X86::Instruction&) { TODO(); }
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void SoftCPU::wrap_0xD3_16(const X86::Instruction&) { TODO(); }
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void SoftCPU::wrap_0xD3_32(const X86::Instruction&) { TODO(); }
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}
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