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Kernel: Move x86-specific IRQ controller code to Arch/x86 directory
The PIC and APIC code are specific to x86 platforms, so move them out of the general Interrupts directory to Arch/x86/common/Interrupts directory instead.
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16 changed files with 19 additions and 19 deletions
115
Kernel/Arch/x86/common/Interrupts/APIC.h
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115
Kernel/Arch/x86/common/Interrupts/APIC.h
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/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Time/HardwareTimer.h>
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namespace Kernel {
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class APICTimer;
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struct LocalAPIC {
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u32 apic_id;
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};
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class APIC {
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public:
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static APIC& the();
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static void initialize();
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static bool initialized();
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bool init_bsp();
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void eoi();
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void setup_ap_boot_environment();
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void boot_aps();
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void enable(u32 cpu);
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void init_finished(u32 cpu);
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void broadcast_ipi();
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void send_ipi(u32 cpu);
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static u8 spurious_interrupt_vector();
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Thread* get_idle_thread(u32 cpu) const;
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u32 enabled_processor_count() const { return m_processor_enabled_cnt; }
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APICTimer* initialize_timers(HardwareTimerBase&);
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APICTimer* get_timer() const { return m_apic_timer; }
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enum class TimerMode {
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OneShot,
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Periodic,
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TSCDeadline
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};
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void setup_local_timer(u32, TimerMode, bool);
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u32 get_timer_current_count();
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u32 get_timer_divisor();
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private:
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struct ICRReg {
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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SMI = 0x2,
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NMI = 0x4,
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INIT = 0x5,
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StartUp = 0x6,
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};
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enum DestinationMode {
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Physical = 0x0,
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Logical = 0x1,
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};
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enum Level {
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DeAssert = 0x0,
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Assert = 0x1
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};
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enum class TriggerMode {
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Edge = 0x0,
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Level = 0x1,
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};
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enum DestinationShorthand {
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NoShorthand = 0x0,
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Self = 0x1,
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AllIncludingSelf = 0x2,
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AllExcludingSelf = 0x3,
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};
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u8 vector { 0 };
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u32 destination { 0 };
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DeliveryMode delivery_mode { DeliveryMode::Fixed };
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DestinationMode destination_mode { DestinationMode::Physical };
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Level level { Level::DeAssert };
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TriggerMode trigger_mode { TriggerMode::Edge };
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DestinationShorthand destination_short { DestinationShorthand::NoShorthand };
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u32 x_low() const { return (u32)vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination_short << 18); }
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u32 x_high() const { return destination << 24; }
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u64 x2_value() const { return ((u64)destination << 32) | x_low(); }
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};
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OwnPtr<Memory::Region> m_apic_base;
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Vector<OwnPtr<Processor>> m_ap_processor_info;
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Vector<OwnPtr<Memory::Region>> m_ap_temporary_boot_stacks;
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Vector<Thread*> m_ap_idle_threads;
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OwnPtr<Memory::Region> m_ap_boot_environment;
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Atomic<u8> m_apic_ap_count { 0 };
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Atomic<u8> m_apic_ap_continue { 0 };
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u32 m_processor_cnt { 0 };
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u32 m_processor_enabled_cnt { 0 };
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APICTimer* m_apic_timer { nullptr };
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bool m_is_x2 { false };
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static PhysicalAddress get_base();
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void set_base(PhysicalAddress const& base);
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void write_register(u32 offset, u32 value);
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u32 read_register(u32 offset);
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void set_lvt(u32 offset, u8 interrupt);
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void set_siv(u32 offset, u8 interrupt);
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void wait_for_pending_icr();
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void write_icr(ICRReg const& icr);
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void do_boot_aps();
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};
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}
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