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Kernel: Support all AMD-defined CPUID feature flags for EAX=80000001h

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We're now able to detect all the AMD-defined CPUID feature flags from
ECX/EDX for EAX=80000001h :^)
This commit is contained in:
Linus Groh 2022-03-27 15:36:47 +01:00 • committed by Andreas Kling
parent 96e6420d8d
commit 1e82c2708d
3 changed files with 167 additions and 6 deletions
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44
Kernel/Arch/x86/CPUID.h
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@ -195,14 +195,46 @@ AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
IA32_ARCH_CAPABILITIES = CPUFeature(1u) << 152u, // IA32_ARCH_CAPABILITIES MSR
IA32_CORE_CAPABILITIES = CPUFeature(1u) << 153u, // IA32_CORE_CAPABILITIES MSR
SSBD = CPUFeature(1u) << 154u, // Speculative Store Bypass Disable
/* EAX=80000001h, ECX */ //
LAHF_LM = CPUFeature(1u) << 155u, // LAHF/SAHF in long mode
CMP_LEGACY = CPUFeature(1u) << 156u, // Hyperthreading not valid
SVM = CPUFeature(1u) << 157u, // Secure Virtual Machine
EXTAPIC = CPUFeature(1u) << 158u, // Extended APIC Space
CR8_LEGACY = CPUFeature(1u) << 159u, // CR8 in 32-bit mode
ABM = CPUFeature(1u) << 160u, // Advanced Bit Manipulation
SSE4A = CPUFeature(1u) << 161u, // SSE4a
MISALIGNSSE = CPUFeature(1u) << 162u, // Misaligned SSE Mode
_3DNOWPREFETCH = CPUFeature(1u) << 163u, // PREFETCH and PREFETCHW Instructions
OSVW = CPUFeature(1u) << 164u, // OS Visible Workaround
IBS = CPUFeature(1u) << 165u, // Instruction Based Sampling
XOP = CPUFeature(1u) << 166u, // XOP instruction set
SKINIT = CPUFeature(1u) << 167u, // SKINIT/STGI Instructions
WDT = CPUFeature(1u) << 168u, // Watchdog timer
LWP = CPUFeature(1u) << 169u, // Light Weight Profiling
FMA4 = CPUFeature(1u) << 170u, // FMA4 instruction set
TCE = CPUFeature(1u) << 171u, // Translation Cache Extension
NODEID_MSR = CPUFeature(1u) << 172u, // NodeID MSR
TBM = CPUFeature(1u) << 173u, // Trailing Bit Manipulation
TOPOEXT = CPUFeature(1u) << 174u, // Topology Extensions
PERFCTR_CORE = CPUFeature(1u) << 175u, // Core Performance Counter Extensions
PERFCTR_NB = CPUFeature(1u) << 176u, // NB Performance Counter Extensions
DBX = CPUFeature(1u) << 177u, // Data Breakpoint Extensions
PERFTSC = CPUFeature(1u) << 178u, // Performance TSC
PCX_L2I = CPUFeature(1u) << 179u, // L2I Performance Counter Extensions
/* EAX=80000001h, EDX */ //
SYSCALL = CPUFeature(1u) << 155u, // SYSCALL/SYSRET Instructions
NX = CPUFeature(1u) << 156u, // NX bit
RDTSCP = CPUFeature(1u) << 157u, // RDTSCP Instruction
LM = CPUFeature(1u) << 158u, // Long Mode
SYSCALL = CPUFeature(1u) << 180u, // SYSCALL/SYSRET Instructions
MP = CPUFeature(1u) << 181u, // Multiprocessor Capable
NX = CPUFeature(1u) << 182u, // NX bit
MMXEXT = CPUFeature(1u) << 183u, // Extended MMX
FXSR_OPT = CPUFeature(1u) << 184u, // FXSAVE/FXRSTOR Optimizations
PDPE1GB = CPUFeature(1u) << 185u, // Gigabyte Pages
RDTSCP = CPUFeature(1u) << 186u, // RDTSCP Instruction
LM = CPUFeature(1u) << 187u, // Long Mode
_3DNOWEXT = CPUFeature(1u) << 188u, // Extended 3DNow!
_3DNOW = CPUFeature(1u) << 189u, // 3DNow!
/* EAX=80000007h, EDX */ //
CONSTANT_TSC = CPUFeature(1u) << 159u, // Invariant TSC
NONSTOP_TSC = CPUFeature(1u) << 160u, // Invariant TSC
CONSTANT_TSC = CPUFeature(1u) << 190u, // Invariant TSC
NONSTOP_TSC = CPUFeature(1u) << 191u, // Invariant TSC
__End = CPUFeature(1u) << 255u);
StringView cpu_feature_to_string_view(CPUFeature::Type const&);