RGBCube/serenity
1
Fork 0
mirror of https://github.com/RGBCube/serenity synced 2025-05-31 07:58:11 +00:00
Code Issues Activity Actions

Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^)

Browse source 
These are added as properties of the "caches" object to each processor,
if available.
This commit is contained in:
Linus Groh 2022-05-28 21:14:08 +01:00 • committed by Andreas Kling
parent 5c79681611
commit 20e2e39fcc
3 changed files with 84 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

22
Kernel/GlobalProcessExposed.cpp
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
* Copyright (c) 2022, Linus Groh <linusg@serenityos.org>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
@ -639,6 +640,27 @@ private:
TRY(obj.add("type", info.type()));
TRY(obj.add("brand", info.brand_string()));
auto caches = TRY(obj.add_object("caches"));
auto add_cache_info = [&](StringView name, ProcessorInfo::Cache const& cache) -> ErrorOr<void> {
auto cache_object = TRY(caches.add_object(name));
TRY(cache_object.add("size", cache.size));
TRY(cache_object.add("line_size", cache.line_size));
TRY(cache_object.finish());
return {};
};
if (info.l1_data_cache().has_value())
TRY(add_cache_info("l1_data", *info.l1_data_cache()));
if (info.l1_data_cache().has_value())
TRY(add_cache_info("l1_instruction", *info.l1_instruction_cache()));
if (info.l1_data_cache().has_value())
TRY(add_cache_info("l2", *info.l2_cache()));
if (info.l1_data_cache().has_value())
TRY(add_cache_info("l3", *info.l3_cache()));
TRY(caches.finish());
TRY(obj.finish());
return {};
}));