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https://github.com/RGBCube/serenity
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Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^)
These are added as properties of the "caches" object to each processor, if available.
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5c79681611
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3 changed files with 84 additions and 0 deletions
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@ -21,6 +21,11 @@ class ProcessorInfo {
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public:
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public:
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ProcessorInfo(Processor const& processor);
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ProcessorInfo(Processor const& processor);
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struct Cache {
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u64 size;
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u64 line_size;
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};
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StringView vendor_id_string() const { return m_vendor_id_string->view(); }
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StringView vendor_id_string() const { return m_vendor_id_string->view(); }
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StringView hypervisor_vendor_id_string() const { return m_hypervisor_vendor_id_string->view(); }
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StringView hypervisor_vendor_id_string() const { return m_hypervisor_vendor_id_string->view(); }
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StringView brand_string() const { return m_brand_string->view(); }
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StringView brand_string() const { return m_brand_string->view(); }
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@ -30,6 +35,10 @@ public:
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u32 stepping() const { return m_stepping; }
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u32 stepping() const { return m_stepping; }
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u32 type() const { return m_type; }
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u32 type() const { return m_type; }
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u32 apic_id() const { return m_apic_id; }
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u32 apic_id() const { return m_apic_id; }
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Optional<Cache> const& l1_data_cache() const { return m_l1_data_cache; }
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Optional<Cache> const& l1_instruction_cache() const { return m_l1_instruction_cache; }
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Optional<Cache> const& l2_cache() const { return m_l2_cache; }
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Optional<Cache> const& l3_cache() const { return m_l3_cache; }
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void set_apic_id(u32 apic_id) { m_apic_id = apic_id; }
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void set_apic_id(u32 apic_id) { m_apic_id = apic_id; }
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@ -39,6 +48,8 @@ private:
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static NonnullOwnPtr<KString> build_brand_string();
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static NonnullOwnPtr<KString> build_brand_string();
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static NonnullOwnPtr<KString> build_features_string(Processor const&);
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static NonnullOwnPtr<KString> build_features_string(Processor const&);
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void populate_cache_sizes();
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NonnullOwnPtr<KString> m_vendor_id_string;
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NonnullOwnPtr<KString> m_vendor_id_string;
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NonnullOwnPtr<KString> m_hypervisor_vendor_id_string;
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NonnullOwnPtr<KString> m_hypervisor_vendor_id_string;
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NonnullOwnPtr<KString> m_brand_string;
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NonnullOwnPtr<KString> m_brand_string;
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@ -48,6 +59,11 @@ private:
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u32 m_stepping { 0 };
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u32 m_stepping { 0 };
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u32 m_type { 0 };
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u32 m_type { 0 };
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u32 m_apic_id { 0 };
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u32 m_apic_id { 0 };
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Optional<Cache> m_l1_data_cache;
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Optional<Cache> m_l1_instruction_cache;
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Optional<Cache> m_l2_cache;
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Optional<Cache> m_l3_cache;
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};
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};
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}
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}
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@ -36,6 +36,8 @@ ProcessorInfo::ProcessorInfo(Processor const& processor)
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m_display_family = family;
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m_display_family = family;
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m_display_model = model;
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m_display_model = model;
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}
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}
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populate_cache_sizes();
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}
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}
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static void emit_u32(StringBuilder& builder, u32 value)
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static void emit_u32(StringBuilder& builder, u32 value)
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@ -110,4 +112,48 @@ NonnullOwnPtr<KString> ProcessorInfo::build_features_string(Processor const& pro
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return KString::must_create(builder.string_view());
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return KString::must_create(builder.string_view());
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}
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}
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void ProcessorInfo::populate_cache_sizes()
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{
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u32 max_extended_leaf = CPUID(0x80000000).eax();
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if (max_extended_leaf < 0x80000005)
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return;
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auto l1_cache_info = CPUID(0x80000005);
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// NOTE: Except for L2, these are not available on Intel CPUs in this form and return 0 for each register in that case.
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if (l1_cache_info.ecx() != 0) {
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m_l1_data_cache = Cache {
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.size = ((l1_cache_info.ecx() >> 24) & 0xff) * KiB,
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.line_size = l1_cache_info.ecx() & 0xff,
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};
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}
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if (l1_cache_info.edx() != 0) {
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m_l1_instruction_cache = Cache {
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.size = ((l1_cache_info.edx() >> 24) & 0xff) * KiB,
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.line_size = l1_cache_info.edx() & 0xff,
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};
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}
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if (max_extended_leaf < 0x80000006)
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return;
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auto l2_l3_cache_info = CPUID(0x80000006);
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if (l2_l3_cache_info.ecx() != 0) {
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m_l2_cache = Cache {
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.size = ((l2_l3_cache_info.ecx() >> 16) & 0xffff) * KiB,
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.line_size = l2_l3_cache_info.ecx() & 0xff,
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};
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}
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if (l2_l3_cache_info.edx() != 0) {
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m_l3_cache = Cache {
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.size = (static_cast<u64>((l2_l3_cache_info.edx() >> 18)) & 0x3fff) * 512 * KiB,
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.line_size = l2_l3_cache_info.edx() & 0xff,
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};
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}
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}
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}
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}
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* Copyright (c) 2022, Linus Groh <linusg@serenityos.org>
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*
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*
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* SPDX-License-Identifier: BSD-2-Clause
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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*/
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@ -639,6 +640,27 @@ private:
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TRY(obj.add("type", info.type()));
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TRY(obj.add("type", info.type()));
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TRY(obj.add("brand", info.brand_string()));
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TRY(obj.add("brand", info.brand_string()));
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auto caches = TRY(obj.add_object("caches"));
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auto add_cache_info = [&](StringView name, ProcessorInfo::Cache const& cache) -> ErrorOr<void> {
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auto cache_object = TRY(caches.add_object(name));
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TRY(cache_object.add("size", cache.size));
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TRY(cache_object.add("line_size", cache.line_size));
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TRY(cache_object.finish());
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return {};
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};
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if (info.l1_data_cache().has_value())
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TRY(add_cache_info("l1_data", *info.l1_data_cache()));
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if (info.l1_data_cache().has_value())
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TRY(add_cache_info("l1_instruction", *info.l1_instruction_cache()));
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if (info.l1_data_cache().has_value())
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TRY(add_cache_info("l2", *info.l2_cache()));
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if (info.l1_data_cache().has_value())
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TRY(add_cache_info("l3", *info.l3_cache()));
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TRY(caches.finish());
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TRY(obj.finish());
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TRY(obj.finish());
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return {};
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return {};
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}));
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}));
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