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https://github.com/RGBCube/serenity
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Kernel: Fixing PCI MMIO access mechanism
During initialization of PCI MMIO access mechanism we ensure that we have an allocation from the kernel virtual address space that cannot be taken by other components in the OS. Also, now we ensure that interrupts are disabled so mapping the region doesn't fail. In order to reduce overhead, map_device() will map the requested PCI address only if it's not mapped already. The run script has been changed so now we can boot a Q35 machine, that supports PCI ECAM. To ensure we will be able to load the machine, a PIIX3 IDE controller was added to the Q35 machine configuration in the run script. An AHCI controller was added to the i440fx machine configuration.
This commit is contained in:
Liav A
Andreas Kling
parent
5e430e4eb4
commit
2a4a19aed8
4 changed files with 110 additions and 24 deletions
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@ -29,11 +29,13 @@ void PCI::MMIOAccess::initialize(ACPI_RAW::MCFG& mcfg)
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PCI::MMIOAccess::MMIOAccess(ACPI_RAW::MCFG& raw_mcfg)
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: m_mcfg(raw_mcfg)
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, m_segments(*new HashMap<u16, MMIOSegment*>())
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, m_mapped_address(ChangeableAddress(0xFFFF, 0xFF, 0xFF, 0xFF))
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{
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kprintf("PCI: Using MMIO Mechanism for PCI Configuartion Space Access\n");
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m_mmio_segment = MM.allocate_kernel_region(PAGE_ROUND_UP(PCI_MMIO_CONFIG_SPACE_SIZE), "PCI MMIO", Region::Access::Read | Region::Access::Write);
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m_mmio_window = *AnonymousVMObject::create_with_size(PAGE_ROUND_UP(PCI_MMIO_CONFIG_SPACE_SIZE));
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m_mmio_window_region = MM.allocate_kernel_region_with_vmobject(*m_mmio_window, m_mmio_window->size(), "PCI MMIO", Region::Access::Read | Region::Access::Write);
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OwnPtr<Region> checkup_region = MM.allocate_kernel_region((PAGE_SIZE * 2), "PCI MCFG Checkup", Region::Access::Read | Region::Access::Write);
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auto checkup_region = MM.allocate_kernel_region((PAGE_SIZE * 2), "PCI MCFG Checkup", Region::Access::Read | Region::Access::Write);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Checking MCFG Table length to choose the correct mapping size\n");
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#endif
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@ -63,82 +65,97 @@ PCI::MMIOAccess::MMIOAccess(ACPI_RAW::MCFG& raw_mcfg)
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}
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mcfg_region->unmap();
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kprintf("PCI: MMIO segments - %d\n", m_segments.size());
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InterruptDisabler disabler;
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#ifdef PCI_DEBUG
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dbgprintf("PCI: mapped address (%w:%b:%b.%b)\n", m_mapped_address.seg(), m_mapped_address.bus(), m_mapped_address.slot(), m_mapped_address.function());
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#endif
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map_device(Address(0, 0, 0, 0));
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Default mapped address (%w:%b:%b.%b)\n", m_mapped_address.seg(), m_mapped_address.bus(), m_mapped_address.slot(), m_mapped_address.function());
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#endif
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}
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void PCI::MMIOAccess::map_device(Address address)
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{
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if (m_mapped_address == address)
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return;
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// FIXME: Map and put some lock!
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Mapping Device @ pci (%d:%d:%d:%d)\n", address.seg(), address.bus(), address.slot(), address.function());
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#endif
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ASSERT_INTERRUPTS_DISABLED();
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ASSERT(m_segments.contains(address.seg()));
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auto segment = m_segments.get(address.seg());
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PhysicalAddress segment_lower_addr = segment.value()->get_paddr();
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PhysicalAddress device_physical_mmio_space = segment_lower_addr.offset(
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PCI_MMIO_CONFIG_SPACE_SIZE * address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * address.slot() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS) * (address.bus() - segment.value()->get_start_bus()));
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Mapping (%d:%d:%d:%d), V 0x%x, P 0x%x\n", address.seg(), address.bus(), address.slot(), address.function(), m_mmio_segment->vaddr().get(), device_physical_mmio_space.get());
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dbgprintf("PCI: Mapping device @ pci (%w:%b:%b.%b), V 0x%x, P 0x%x\n", address.seg(), address.bus(), address.slot(), address.function(), m_mmio_window_region->vaddr().get(), device_physical_mmio_space.get());
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#endif
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MM.map_for_kernel(m_mmio_segment->vaddr(), device_physical_mmio_space, false);
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MM.map_for_kernel(m_mmio_window_region->vaddr(), device_physical_mmio_space);
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m_mapped_address = address;
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}
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u8 PCI::MMIOAccess::read8_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Reading field %u, Address(%u:%u:%u:%u)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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dbgprintf("PCI: Reading field %u, Address(%w:%b:%b.%b)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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#endif
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map_device(address);
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return *((u8*)(m_mmio_segment->vaddr().get() + (field & 0xfff)));
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return *((u8*)(m_mmio_window_region->vaddr().get() + (field & 0xfff)));
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}
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u16 PCI::MMIOAccess::read16_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ASSERT(field < 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Reading field %u, Address(%u:%u:%u:%u)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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dbgprintf("PCI: Reading field %u, Address(%w:%b:%b.%b)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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#endif
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map_device(address);
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return *((u16*)(m_mmio_segment->vaddr().get() + (field & 0xfff)));
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return *((u16*)(m_mmio_window_region->vaddr().get() + (field & 0xfff)));
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}
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u32 PCI::MMIOAccess::read32_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xffc);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Reading field %u, Address(%u:%u:%u:%u)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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dbgprintf("PCI: Reading field %u, Address(%w:%b:%b.%b)\n", field, address.seg(), address.bus(), address.slot(), address.function());
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#endif
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map_device(address);
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return *((u32*)(m_mmio_segment->vaddr().get() + (field & 0xfff)));
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return *((u32*)(m_mmio_window_region->vaddr().get() + (field & 0xfff)));
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}
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void PCI::MMIOAccess::write8_field(Address address, u32 field, u8 value)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Write to field %u, Address(%u:%u:%u:%u), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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dbgprintf("PCI: Write to field %u, Address(%w:%b:%b.%b), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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#endif
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map_device(address);
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*((u8*)(m_mmio_segment->vaddr().get() + (field & 0xfff))) = value;
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*((u8*)(m_mmio_window_region->vaddr().get() + (field & 0xfff))) = value;
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}
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void PCI::MMIOAccess::write16_field(Address address, u32 field, u16 value)
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{
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InterruptDisabler disabler;
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ASSERT(field < 0xfff);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Write to field %u, Address(%u:%u:%u:%u), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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dbgprintf("PCI: Write to field %u, Address(%w:%b:%b.%b), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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#endif
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map_device(address);
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*((u16*)(m_mmio_segment->vaddr().get() + (field & 0xfff))) = value;
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*((u16*)(m_mmio_window_region->vaddr().get() + (field & 0xfff))) = value;
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}
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void PCI::MMIOAccess::write32_field(Address address, u32 field, u32 value)
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{
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InterruptDisabler disabler;
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ASSERT(field <= 0xffc);
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Write to field %u, Address(%u:%u:%u:%u), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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dbgprintf("PCI: Write to field %u, Address(%w:%b:%b.%b), value 0x%x\n", field, address.seg(), address.bus(), address.slot(), address.function(), value);
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#endif
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map_device(address);
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*((u32*)(m_mmio_segment->vaddr().get() + (field & 0xfff))) = value;
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*((u32*)(m_mmio_window_region->vaddr().get() + (field & 0xfff))) = value;
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}
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void PCI::MMIOAccess::enumerate_all(Function<void(Address, ID)>& callback)
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@ -167,7 +184,7 @@ void PCI::MMIOAccess::mmap(VirtualAddress vaddr, PhysicalAddress paddr, u32 leng
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unsigned i = 0;
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while (length >= PAGE_SIZE) {
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MM.map_for_kernel(VirtualAddress(vaddr.offset(i * PAGE_SIZE).get()), PhysicalAddress(paddr.offset(i * PAGE_SIZE).get()));
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#ifdef ACPI_DEBUG
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#ifdef PCI_DEBUG
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dbgprintf("PCI: map - V 0x%x -> P 0x%x\n", vaddr.offset(i * PAGE_SIZE).get(), paddr.offset(i * PAGE_SIZE).get());
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#endif
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length -= PAGE_SIZE;
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@ -176,7 +193,7 @@ void PCI::MMIOAccess::mmap(VirtualAddress vaddr, PhysicalAddress paddr, u32 leng
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if (length > 0) {
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MM.map_for_kernel(vaddr.offset(i * PAGE_SIZE), paddr.offset(i * PAGE_SIZE), true);
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}
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#ifdef ACPI_DEBUG
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#ifdef PCI_DEBUG
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dbgprintf("PCI: Finished mapping\n");
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#endif
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}
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