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https://github.com/RGBCube/serenity
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Kernel/Storage: Merge IDE functionality from BusMasterChannel to Channel
This simplifies the flow of how things work currently and is a step for more improvements in the next commits.
This commit is contained in:
Liav A
Linus Groh
parent
ade672c576
commit
2c987367e6
11 changed files with 294 additions and 358 deletions
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@ -8,6 +8,7 @@
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#include <AK/Singleton.h>
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#include <AK/StringView.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Process.h>
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#include <Kernel/Sections.h>
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@ -42,7 +43,17 @@ RefPtr<StorageDevice> IDEChannel::slave_device() const
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return m_slave;
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}
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UNMAP_AFTER_INIT void IDEChannel::initialize()
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UNMAP_AFTER_INIT void IDEChannel::initialize_with_isa_controller(Badge<ISAIDEController>, bool force_pio)
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{
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initialize(force_pio);
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}
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UNMAP_AFTER_INIT void IDEChannel::initialize_with_pci_controller(Badge<PCIIDEController>, bool force_pio)
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{
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initialize(force_pio);
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}
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UNMAP_AFTER_INIT void IDEChannel::initialize(bool force_pio)
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{
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disable_irq();
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dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
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@ -75,6 +86,31 @@ UNMAP_AFTER_INIT void IDEChannel::initialize()
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// Note: calling to detect_disks could generate an interrupt, clear it if that's the case
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clear_pending_interrupts();
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if (!force_pio) {
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m_dma_enabled = true;
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VERIFY(m_io_group.bus_master_base().has_value());
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// Let's try to set up DMA transfers.
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{
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auto region_or_error = MM.allocate_dma_buffer_page("IDE PRDT"sv, Memory::Region::Access::ReadWrite, m_prdt_page);
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if (region_or_error.is_error())
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TODO();
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m_prdt_region = region_or_error.release_value();
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VERIFY(!m_prdt_page.is_null());
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}
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{
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auto region_or_error = MM.allocate_dma_buffer_page("IDE DMA region"sv, Memory::Region::Access::ReadWrite, m_dma_buffer_page);
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if (region_or_error.is_error())
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TODO();
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m_dma_buffer_region = region_or_error.release_value();
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VERIFY(!m_dma_buffer_page.is_null());
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}
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prdt().end_of_table = 0x8000;
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// clear bus master interrupt status
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 4);
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}
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}
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(IDEController const& controller, u8 irq, IOAddressGroup io_group, ChannelType type)
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@ -83,7 +119,6 @@ UNMAP_AFTER_INIT IDEChannel::IDEChannel(IDEController const& controller, u8 irq,
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, m_io_group(io_group)
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, m_parent_controller(controller)
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{
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initialize();
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}
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(IDEController const& controller, IOAddressGroup io_group, ChannelType type)
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@ -92,7 +127,6 @@ UNMAP_AFTER_INIT IDEChannel::IDEChannel(IDEController const& controller, IOAddre
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, m_io_group(io_group)
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, m_parent_controller(controller)
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{
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initialize();
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}
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void IDEChannel::clear_pending_interrupts() const
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@ -113,13 +147,20 @@ void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool is_slave,
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m_current_request_block_index = 0;
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m_current_request_flushing_cache = false;
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if (m_dma_enabled) {
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if (request.request_type() == AsyncBlockDeviceRequest::Read)
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ata_read_sectors_with_dma(is_slave, capabilities);
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else
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ata_write_sectors_with_dma(is_slave, capabilities);
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return;
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}
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if (request.request_type() == AsyncBlockDeviceRequest::Read)
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ata_read_sectors(is_slave, capabilities);
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ata_read_sectors_with_pio(is_slave, capabilities);
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else
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ata_write_sectors(is_slave, capabilities);
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ata_write_sectors_with_pio(is_slave, capabilities);
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}
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void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult result)
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void IDEChannel::complete_dma_transaction(AsyncDeviceRequest::RequestResult result)
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{
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// NOTE: this may be called from the interrupt handler!
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VERIFY(m_current_request);
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@ -130,7 +171,48 @@ void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult resu
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// which could cause page faults. Note that this may be called immediately
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// before Processor::deferred_call_queue returns!
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auto work_item_creation_result = g_io_work->try_queue([this, result]() {
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dbgln_if(PATA_DEBUG, "IDEChannel::complete_current_request result: {}", (int)result);
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dbgln_if(PATA_DEBUG, "IDEChannel::complete_dma_transaction result: {}", (int)result);
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SpinlockLocker lock(m_request_lock);
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VERIFY(m_current_request);
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auto current_request = m_current_request;
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m_current_request.clear();
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if (result == AsyncDeviceRequest::Success) {
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if (current_request->request_type() == AsyncBlockDeviceRequest::Read) {
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if (auto result = current_request->write_to_buffer(current_request->buffer(), m_dma_buffer_region->vaddr().as_ptr(), current_request->buffer_size()); result.is_error()) {
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lock.unlock();
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current_request->complete(AsyncDeviceRequest::MemoryFault);
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return;
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}
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}
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// I read somewhere that this may trigger a cache flush so let's do it.
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VERIFY(m_io_group.bus_master_base().has_value());
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
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}
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lock.unlock();
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current_request->complete(result);
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});
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if (work_item_creation_result.is_error()) {
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auto current_request = m_current_request;
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m_current_request.clear();
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current_request->complete(AsyncDeviceRequest::OutOfMemory);
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}
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}
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void IDEChannel::complete_pio_transaction(AsyncDeviceRequest::RequestResult result)
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{
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// NOTE: this may be called from the interrupt handler!
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VERIFY(m_current_request);
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VERIFY(m_request_lock.is_locked());
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// Now schedule reading back the buffer as soon as we leave the irq handler.
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// This is important so that we can safely write the buffer back,
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// which could cause page faults. Note that this may be called immediately
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// before Processor::deferred_call_queue returns!
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auto work_item_creation_result = g_io_work->try_queue([this, result]() {
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dbgln_if(PATA_DEBUG, "IDEChannel::complete_pio_transaction result: {}", (int)result);
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MutexLocker locker(m_lock);
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VERIFY(m_current_request);
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auto current_request = m_current_request;
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@ -193,7 +275,47 @@ void IDEChannel::try_disambiguate_error()
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}
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}
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bool IDEChannel::handle_irq(RegisterState const&)
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bool IDEChannel::handle_irq_for_dma_transaction()
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{
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u8 status = m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();
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m_entropy_source.add_random_event(status);
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VERIFY(m_io_group.bus_master_base().has_value());
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u8 bstatus = m_io_group.bus_master_base().value().offset(2).in<u8>();
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if (!(bstatus & 0x4)) {
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// interrupt not from this device, ignore
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dbgln_if(PATA_DEBUG, "IDEChannel: ignore interrupt");
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return false;
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}
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// clear bus master interrupt status
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 4);
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SpinlockLocker lock(m_request_lock);
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dbgln_if(PATA_DEBUG, "IDEChannel: interrupt: DRQ={}, BSY={}, DRDY={}",
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(status & ATA_SR_DRQ) != 0,
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(status & ATA_SR_BSY) != 0,
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(status & ATA_SR_DRDY) != 0);
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if (!m_current_request) {
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dbgln("IDEChannel: IRQ but no pending request!");
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return false;
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}
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if (status & ATA_SR_ERR) {
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print_ide_status(status);
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m_device_error = m_io_group.io_base().offset(ATA_REG_ERROR).in<u8>();
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dbgln("IDEChannel: Error {:#02x}!", (u8)m_device_error);
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try_disambiguate_error();
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complete_dma_transaction(AsyncDeviceRequest::Failure);
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return true;
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}
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m_device_error = 0;
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complete_dma_transaction(AsyncDeviceRequest::Success);
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return true;
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}
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bool IDEChannel::handle_irq_for_pio_transaction()
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{
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u8 status = m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();
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@ -215,7 +337,7 @@ bool IDEChannel::handle_irq(RegisterState const&)
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m_device_error = m_io_group.io_base().offset(ATA_REG_ERROR).in<u8>();
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dbgln("IDEChannel: Error {:#02x}!", (u8)m_device_error);
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try_disambiguate_error();
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complete_current_request(AsyncDeviceRequest::Failure);
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complete_pio_transaction(AsyncDeviceRequest::Failure);
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return true;
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}
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m_device_error = 0;
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@ -229,9 +351,9 @@ bool IDEChannel::handle_irq(RegisterState const&)
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if (m_current_request->request_type() == AsyncBlockDeviceRequest::Read) {
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dbgln_if(PATA_DEBUG, "IDEChannel: Read block {}/{}", m_current_request_block_index, m_current_request->block_count());
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if (ata_do_read_sector()) {
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if (ata_do_pio_read_sector()) {
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if (++m_current_request_block_index >= m_current_request->block_count()) {
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complete_current_request(AsyncDeviceRequest::Success);
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complete_pio_transaction(AsyncDeviceRequest::Success);
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return;
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}
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// Wait for the next block
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@ -247,10 +369,10 @@ bool IDEChannel::handle_irq(RegisterState const&)
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(ATA_CMD_CACHE_FLUSH);
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} else {
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// Read next block
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ata_do_write_sector();
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ata_do_pio_write_sector();
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}
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} else {
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complete_current_request(AsyncDeviceRequest::Success);
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complete_pio_transaction(AsyncDeviceRequest::Success);
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}
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}
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});
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@ -262,6 +384,13 @@ bool IDEChannel::handle_irq(RegisterState const&)
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return true;
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}
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bool IDEChannel::handle_irq(RegisterState const&)
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{
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if (!m_dma_enabled)
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return handle_irq_for_pio_transaction();
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return handle_irq_for_dma_transaction();
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}
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static void io_delay()
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{
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for (int i = 0; i < 4; ++i)
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@ -467,11 +596,14 @@ void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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send_ata_io_command(lba_mode, direction);
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if (m_dma_enabled)
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send_ata_dma_command(lba_mode, direction);
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else
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send_ata_pio_command(lba_mode, direction);
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enable_irq();
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}
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void IDEChannel::send_ata_io_command(LBAMode lba_mode, Direction direction) const
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void IDEChannel::send_ata_pio_command(LBAMode lba_mode, Direction direction) const
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{
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if (lba_mode != LBAMode::FortyEightBit) {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO : ATA_CMD_WRITE_PIO);
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@ -480,12 +612,12 @@ void IDEChannel::send_ata_io_command(LBAMode lba_mode, Direction direction) cons
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}
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}
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bool IDEChannel::ata_do_read_sector()
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bool IDEChannel::ata_do_pio_read_sector()
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{
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VERIFY(m_lock.is_locked());
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VERIFY(m_request_lock.is_locked());
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VERIFY(!m_current_request.is_null());
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_do_read_sector");
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_do_pio_read_sector");
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auto& request = *m_current_request;
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auto block_size = m_current_request->block_size();
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auto out_buffer = request.buffer().offset(m_current_request_block_index * block_size);
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@ -496,26 +628,25 @@ bool IDEChannel::ata_do_read_sector()
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});
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if (result.is_error()) {
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// TODO: Do we need to abort the PATA read if this wasn't the last block?
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complete_current_request(AsyncDeviceRequest::MemoryFault);
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complete_pio_transaction(AsyncDeviceRequest::MemoryFault);
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return false;
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}
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return true;
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}
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// FIXME: This doesn't quite work and locks up reading LBA 3.
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void IDEChannel::ata_read_sectors(bool slave_request, u16 capabilities)
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void IDEChannel::ata_read_sectors_with_pio(bool slave_request, u16 capabilities)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(!m_current_request.is_null());
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VERIFY(m_current_request->block_count() <= 256);
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SpinlockLocker m_lock(m_request_lock);
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors");
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors_with_pio");
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dbgln_if(PATA_DEBUG, "IDEChannel: Reading {} sector(s) @ LBA {}", m_current_request->block_count(), m_current_request->block_index());
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ata_access(Direction::Read, slave_request, m_current_request->block_index(), m_current_request->block_count(), capabilities);
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}
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void IDEChannel::ata_do_write_sector()
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void IDEChannel::ata_do_pio_write_sector()
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{
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VERIFY(m_lock.is_locked());
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VERIFY(m_request_lock.is_locked());
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@ -538,11 +669,11 @@ void IDEChannel::ata_do_write_sector()
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return readonly_bytes.size();
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});
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if (result.is_error())
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complete_current_request(AsyncDeviceRequest::MemoryFault);
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complete_pio_transaction(AsyncDeviceRequest::MemoryFault);
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}
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// FIXME: I'm assuming this doesn't work based on the fact PIO read doesn't work.
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void IDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
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void IDEChannel::ata_write_sectors_with_pio(bool slave_request, u16 capabilities)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(!m_current_request.is_null());
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@ -551,6 +682,92 @@ void IDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
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SpinlockLocker m_lock(m_request_lock);
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dbgln_if(PATA_DEBUG, "IDEChannel: Writing {} sector(s) @ LBA {}", m_current_request->block_count(), m_current_request->block_index());
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ata_access(Direction::Write, slave_request, m_current_request->block_index(), m_current_request->block_count(), capabilities);
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ata_do_write_sector();
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ata_do_pio_write_sector();
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}
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void IDEChannel::send_ata_dma_command(LBAMode lba_mode, Direction direction) const
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{
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if (lba_mode != LBAMode::FortyEightBit) {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA : ATA_CMD_WRITE_DMA);
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} else {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA_EXT : ATA_CMD_WRITE_DMA_EXT);
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}
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}
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void IDEChannel::ata_read_sectors_with_dma(bool slave_request, u16 capabilities)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(!m_current_request.is_null());
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VERIFY(m_current_request->block_count() <= 256);
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SpinlockLocker m_lock(m_request_lock);
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors_with_dma ({} x {})", m_current_request->block_index(), m_current_request->block_count());
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// Note: This is a fix for a quirk for an IDE controller on ICH7 machine.
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// We need to select the drive and then we wait 10 microseconds... and it doesn't hurt anything
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m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | ((slave_request ? 1 : 0) << 4));
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IO::delay(10);
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prdt().offset = m_dma_buffer_page->paddr().get();
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prdt().size = 512 * m_current_request->block_count();
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VERIFY(prdt().size <= PAGE_SIZE);
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VERIFY(m_io_group.bus_master_base().has_value());
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// Stop bus master
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m_io_group.bus_master_base().value().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().value().offset(4).out<u32>(m_prdt_page->paddr().get());
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// Set transfer direction
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m_io_group.bus_master_base().value().out<u8>(0x8);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
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ata_access(Direction::Read, slave_request, m_current_request->block_index(), m_current_request->block_count(), capabilities);
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// Start bus master
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m_io_group.bus_master_base().value().out<u8>(0x9);
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}
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void IDEChannel::ata_write_sectors_with_dma(bool slave_request, u16 capabilities)
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{
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VERIFY(m_lock.is_locked());
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VERIFY(!m_current_request.is_null());
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VERIFY(m_current_request->block_count() <= 256);
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SpinlockLocker m_lock(m_request_lock);
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_write_sectors_with_dma ({} x {})", m_current_request->block_index(), m_current_request->block_count());
|
||||
|
||||
prdt().offset = m_dma_buffer_page->paddr().get();
|
||||
prdt().size = 512 * m_current_request->block_count();
|
||||
|
||||
if (auto result = m_current_request->read_from_buffer(m_current_request->buffer(), m_dma_buffer_region->vaddr().as_ptr(), 512 * m_current_request->block_count()); result.is_error()) {
|
||||
complete_dma_transaction(AsyncDeviceRequest::MemoryFault);
|
||||
return;
|
||||
}
|
||||
|
||||
// Note: This is a fix for a quirk for an IDE controller on ICH7 machine.
|
||||
// We need to select the drive and then we wait 10 microseconds... and it doesn't hurt anything
|
||||
m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | ((slave_request ? 1 : 0) << 4));
|
||||
IO::delay(10);
|
||||
|
||||
VERIFY(prdt().size <= PAGE_SIZE);
|
||||
VERIFY(m_io_group.bus_master_base().has_value());
|
||||
// Stop bus master
|
||||
m_io_group.bus_master_base().value().out<u8>(0);
|
||||
|
||||
// Write the PRDT location
|
||||
m_io_group.bus_master_base().value().offset(4).out<u32>(m_prdt_page->paddr().get());
|
||||
|
||||
// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
|
||||
m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
|
||||
|
||||
ata_access(Direction::Write, slave_request, m_current_request->block_index(), m_current_request->block_count(), capabilities);
|
||||
|
||||
// Start bus master
|
||||
m_io_group.bus_master_base().value().out<u8>(0x1);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue