Kernel/Graphics: Introduce the IntelDisplayConnectorGroup class

In the real world, graphics hardware tend to have multiple display
connectors. However, usually the connectors share one register space but
still keeping different PLL timings and display lanes.
This new class should represent a group of multiple display connectors
working together in the same Intel graphics adapter. This opens an
opportunity to abstract the interface so we could support future Intel
iGPU generations.

This is also a preparation before the driver can support newer devices
and utilize their capabilities.
The mentioned preparation is applied in a these aspects:
1. The code is splitted into more classes to adjust to future expansion.
2 classes are introduced: IntelDisplayPlane and IntelDisplayTranscoder,
so the IntelDisplayPlane controls the plane registers and second class
controls the pipeline (transcoder, encoder) registers. On gen4 it's not
really useful because there are probably one plane and one encoder to
care about, but in future generations, there are likely to be multiple
transcoders and planes to accommodate multi head support.
2. The set_edid_bytes method in the DisplayConnector class can now be
told to not assume the provided EDID bytes are always invalid. Therefore
it can refrain from printing error messages if this flag parameter is
true. This is useful for supporting real hardware situation when on boot
not all ports are connected to a monitor, which can result in floating
bus condition (essentially all the bytes we read are 0xFF).
3. An IntelNativeDisplayConnector could now be set to flag other types
of connections such as eDP (embedded DisplayPort), Analog output, etc.
This is important because on the Intel gen4 graphics we could assume to
have one analog output connector, but on future generations this is very
likely to not be the case, as there might be no VGA outputs, but rather
only an eDP connector which is converted to VGA by a design choice of
the motherboard manufacturer.
4. Add ConnectorIndex to IntelNativeDisplayConnector class - Currently
this is used to verify we always handle the correct connector when doing
modesetting.
Later, it will be used to locate special settings needed when handling
connector requests.
5. Prepare to support more types of display planes. For example, the
Intel Skylake register set for display planes is a bit different, so
let's ensure we can properly support it in the near future.

Kernel/Graphics/Intel/Plane/DisplayPlane.cpp

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <Kernel/Graphics/Intel/Plane/DisplayPlane.h>
+#include <Kernel/PhysicalAddress.h>
+
+namespace Kernel {
+
+IntelDisplayPlane::IntelDisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> plane_registers_mapping)
+    : m_plane_registers(move(plane_registers_mapping))
+{
+}
+
+IntelDisplayPlane::ShadowRegisters IntelDisplayPlane::shadow_registers() const
+{
+    SpinlockLocker locker(m_access_lock);
+    return m_shadow_registers;
+}
+
+ErrorOr<void> IntelDisplayPlane::enable(Badge<IntelDisplayConnectorGroup>)
+{
+    SpinlockLocker locker(m_access_lock);
+    // Note: We use the shadow register so we don't have the already set
+    // settings being lost.
+    m_plane_registers->control = m_shadow_registers.control | (1 << 31);
+    m_shadow_registers.control |= (1 << 31);
+    return {};
+}
+
+bool IntelDisplayPlane::is_enabled(Badge<IntelDisplayConnectorGroup>)
+{
+    SpinlockLocker locker(m_access_lock);
+    return m_shadow_registers.control & (1 << 31);
+}
+
+ErrorOr<void> IntelDisplayPlane::disable(Badge<IntelDisplayConnectorGroup>)
+{
+    SpinlockLocker locker(m_access_lock);
+    // Note: We use the shadow register so we don't have the already set
+    // settings being lost.
+    m_shadow_registers.control &= ~(1 << 31);
+    m_plane_registers->control = m_shadow_registers.control;
+    return {};
+}
+
+}

Kernel/Graphics/Intel/Plane/DisplayPlane.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <AK/RefPtr.h>
+#include <AK/Try.h>
+#include <AK/Types.h>
+#include <Kernel/Graphics/DisplayConnector.h>
+#include <Kernel/Graphics/Intel/Definitions.h>
+#include <Kernel/Locking/Spinlock.h>
+#include <Kernel/Memory/TypedMapping.h>
+
+namespace Kernel {
+
+class IntelDisplayConnectorGroup;
+class IntelDisplayPlane {
+public:
+    enum class PipeSelect {
+        PipeA,
+        PipeB,
+        PipeC,
+        PipeD,
+    };
+
+    // Note: This is used to "cache" all the registers we wrote to, because
+    // we might not be able to read them directly from hardware later.
+    struct ShadowRegisters {
+        u32 control;
+        u32 linear_offset;
+        u32 stride;
+        u32 surface_base;
+    };
+
+public:
+    static ErrorOr<NonnullOwnPtr<IntelDisplayPlane>> create_with_physical_address(PhysicalAddress plane_registers_start_address);
+
+    virtual ErrorOr<void> set_plane_settings(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start, PipeSelect, size_t horizontal_active_pixels_count) = 0;
+    ErrorOr<void> enable(Badge<IntelDisplayConnectorGroup>);
+    bool is_enabled(Badge<IntelDisplayConnectorGroup>);
+    ErrorOr<void> disable(Badge<IntelDisplayConnectorGroup>);
+
+    ShadowRegisters shadow_registers() const;
+
+    virtual ~IntelDisplayPlane() = default;
+
+protected:
+    struct [[gnu::packed]] PlaneRegisters {
+        u32 control;
+        u32 linear_offset;
+        u32 stride;
+        u8 padding[24]; // Note: This might contain other registers, don't touch them.
+        u32 surface_base;
+    };
+
+    explicit IntelDisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping);
+    mutable Spinlock<LockRank::None> m_access_lock;
+    ShadowRegisters m_shadow_registers {};
+    Memory::TypedMapping<PlaneRegisters volatile> m_plane_registers;
+};
+}

Kernel/Graphics/Intel/Plane/G33DisplayPlane.cpp

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <Kernel/Graphics/Intel/Plane/G33DisplayPlane.h>
+#include <Kernel/PhysicalAddress.h>
+
+namespace Kernel {
+
+ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> IntelG33DisplayPlane::create_with_physical_address(PhysicalAddress plane_registers_start_address)
+{
+    auto registers_mapping = TRY(Memory::map_typed<PlaneRegisters volatile>(plane_registers_start_address, sizeof(PlaneRegisters), Memory::Region::Access::ReadWrite));
+    return adopt_nonnull_own_or_enomem(new (nothrow) IntelG33DisplayPlane(move(registers_mapping)));
+}
+
+IntelG33DisplayPlane::IntelG33DisplayPlane(Memory::TypedMapping<PlaneRegisters volatile> registers_mapping)
+    : IntelDisplayPlane(move(registers_mapping))
+{
+}
+
+ErrorOr<void> IntelG33DisplayPlane::set_plane_settings(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start, PipeSelect pipe_select, size_t horizontal_active_pixels_count)
+{
+    SpinlockLocker locker(m_access_lock);
+    VERIFY(((horizontal_active_pixels_count * 4) % 64 == 0));
+    VERIFY(aperture_start < PhysicalAddress(0x1'0000'0000));
+
+    u32 control_value = 0;
+
+    switch (pipe_select) {
+    case PipeSelect::PipeA:
+        control_value |= (0b00 << 24);
+        break;
+    case PipeSelect::PipeB:
+        control_value |= (0b01 << 24);
+        break;
+    case PipeSelect::PipeC:
+        control_value |= (0b10 << 24);
+        break;
+    case PipeSelect::PipeD:
+        control_value |= (0b11 << 24);
+        break;
+    }
+
+    // Note: Set the plane to work with 32 bit BGRX (Ignore Alpha channel).
+    control_value |= (0b0110 << 26);
+
+    m_plane_registers->stride = horizontal_active_pixels_count * 4;
+    m_shadow_registers.stride = horizontal_active_pixels_count * 4;
+    m_plane_registers->linear_offset = 0;
+    m_shadow_registers.linear_offset = 0;
+    m_plane_registers->surface_base = aperture_start.get();
+    m_shadow_registers.surface_base = aperture_start.get();
+    m_plane_registers->control = control_value;
+    m_shadow_registers.control = control_value;
+    return {};
+}
+}

Kernel/Graphics/Intel/Plane/G33DisplayPlane.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <AK/RefPtr.h>
+#include <AK/Try.h>
+#include <AK/Types.h>
+#include <Kernel/Graphics/Intel/Plane/DisplayPlane.h>
+
+namespace Kernel {
+
+class IntelDisplayConnectorGroup;
+class IntelG33DisplayPlane final : public IntelDisplayPlane {
+public:
+    static ErrorOr<NonnullOwnPtr<IntelG33DisplayPlane>> create_with_physical_address(PhysicalAddress plane_registers_start_address);
+
+    virtual ErrorOr<void> set_plane_settings(Badge<IntelDisplayConnectorGroup>, PhysicalAddress aperture_start, PipeSelect, size_t horizontal_active_pixels_count) override;
+
+private:
+    explicit IntelG33DisplayPlane(Memory::TypedMapping<volatile IntelDisplayPlane::PlaneRegisters> plane_registers_mapping);
+};
+}