diff --git a/Kernel/Arch/aarch64/Aarch64Asm.h b/Kernel/Arch/aarch64/Aarch64Asm.h index ceeb362316..858a824cf4 100644 --- a/Kernel/Arch/aarch64/Aarch64Asm.h +++ b/Kernel/Arch/aarch64/Aarch64Asm.h @@ -6,7 +6,7 @@ #pragma once -#include +#include namespace Kernel { diff --git a/Kernel/Arch/aarch64/Aarch64Registers.h b/Kernel/Arch/aarch64/Registers.h similarity index 84% rename from Kernel/Arch/aarch64/Aarch64Registers.h rename to Kernel/Arch/aarch64/Registers.h index 2ba6ff5e70..0319c62c06 100644 --- a/Kernel/Arch/aarch64/Aarch64Registers.h +++ b/Kernel/Arch/aarch64/Registers.h @@ -9,11 +9,11 @@ #include -namespace Kernel { +namespace Kernel::Aarch64 { // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/ID-AA64MMFR0-EL1--AArch64-Memory-Model-Feature-Register-0 // Memory Model Feature Register 0 -struct Aarch64_ID_AA64MMFR0_EL1 { +struct ID_AA64MMFR0_EL1 { int PARange : 4; int ASIDBits : 4; int BigEnd : 4; @@ -30,9 +30,9 @@ struct Aarch64_ID_AA64MMFR0_EL1 { int FGT : 4; int ECV : 4; - static inline Aarch64_ID_AA64MMFR0_EL1 read() + static inline ID_AA64MMFR0_EL1 read() { - Aarch64_ID_AA64MMFR0_EL1 feature_register; + ID_AA64MMFR0_EL1 feature_register; asm("mrs %[value], ID_AA64MMFR0_EL1" : [value] "=r"(feature_register)); @@ -43,7 +43,7 @@ struct Aarch64_ID_AA64MMFR0_EL1 { // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1- // Translation Control Register -struct Aarch64_TCR_EL1 { +struct TCR_EL1 { enum Shareability { NonSharable = 0b00, @@ -130,14 +130,14 @@ struct Aarch64_TCR_EL1 { int DS : 1; int RES0_2 : 4; - static inline void write(Aarch64_TCR_EL1 tcr_el1) + static inline void write(TCR_EL1 tcr_el1) { asm("msr tcr_el1, %[value]" ::[value] "r"(tcr_el1)); } - static inline Aarch64_TCR_EL1 read() + static inline TCR_EL1 read() { - Aarch64_TCR_EL1 tcr_el1; + TCR_EL1 tcr_el1; asm("mrs %[value], tcr_el1_el1" : [value] "=r"(tcr_el1)); @@ -145,16 +145,16 @@ struct Aarch64_TCR_EL1 { return tcr_el1; } - static inline constexpr Aarch64_TCR_EL1 reset_value() + static inline constexpr TCR_EL1 reset_value() { return {}; } }; -static_assert(sizeof(Aarch64_TCR_EL1) == 8); +static_assert(sizeof(TCR_EL1) == 8); // https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/SCTLR-EL1--System-Control-Register--EL1- // System Control Register -struct Aarch64_SCTLR_EL1 { +struct SCTLR_EL1 { int M : 1; int A : 1; int C : 1; @@ -205,14 +205,14 @@ struct Aarch64_SCTLR_EL1 { int EPAN : 1; int _reserved58 : 6 = 0; - static inline void write(Aarch64_SCTLR_EL1 sctlr_el1) + static inline void write(SCTLR_EL1 sctlr_el1) { asm("msr sctlr_el1, %[value]" ::[value] "r"(sctlr_el1)); } - static inline Aarch64_SCTLR_EL1 read() + static inline SCTLR_EL1 read() { - Aarch64_SCTLR_EL1 sctlr; + SCTLR_EL1 sctlr; asm("mrs %[value], sctlr_el1" : [value] "=r"(sctlr)); @@ -220,9 +220,9 @@ struct Aarch64_SCTLR_EL1 { return sctlr; } - static inline constexpr Aarch64_SCTLR_EL1 reset_value() + static inline constexpr SCTLR_EL1 reset_value() { - Aarch64_SCTLR_EL1 system_control_register_el1 = {}; + SCTLR_EL1 system_control_register_el1 = {}; system_control_register_el1.LSMAOE = 1; system_control_register_el1.nTLSMD = 1; system_control_register_el1.SPAN = 1; @@ -230,11 +230,11 @@ struct Aarch64_SCTLR_EL1 { return system_control_register_el1; } }; -static_assert(sizeof(Aarch64_SCTLR_EL1) == 8); +static_assert(sizeof(SCTLR_EL1) == 8); // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register // Hypervisor Configuration Register -struct Aarch64_HCR_EL2 { +struct HCR_EL2 { int VM : 1; int SWIO : 1; int PTW : 1; @@ -280,14 +280,14 @@ struct Aarch64_HCR_EL2 { int AT : 1 = 0; int _reserved45 : 18 = 0; - static inline void write(Aarch64_HCR_EL2 hcr_el2) + static inline void write(HCR_EL2 hcr_el2) { asm("msr hcr_el2, %[value]" ::[value] "r"(hcr_el2)); } - static inline Aarch64_HCR_EL2 read() + static inline HCR_EL2 read() { - Aarch64_HCR_EL2 spsr; + HCR_EL2 spsr; asm("mrs %[value], hcr_el2" : [value] "=r"(spsr)); @@ -295,11 +295,11 @@ struct Aarch64_HCR_EL2 { return spsr; } }; -static_assert(sizeof(Aarch64_HCR_EL2) == 8); +static_assert(sizeof(HCR_EL2) == 8); // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SCR-EL3--Secure-Configuration-Register // Secure Configuration Register -struct Aarch64_SCR_EL3 { +struct SCR_EL3 { int NS : 1; int IRQ : 1; int FIQ : 1; @@ -336,14 +336,14 @@ struct Aarch64_SCR_EL3 { int HXEn : 1; int _reserved39 : 14 = 0; - static inline void write(Aarch64_SCR_EL3 scr_el3) + static inline void write(SCR_EL3 scr_el3) { asm("msr scr_el3, %[value]" ::[value] "r"(scr_el3)); } - static inline Aarch64_SCR_EL3 read() + static inline SCR_EL3 read() { - Aarch64_SCR_EL3 scr; + SCR_EL3 scr; asm("mrs %[value], scr_el3" : [value] "=r"(scr)); @@ -351,9 +351,9 @@ struct Aarch64_SCR_EL3 { return scr; } }; -static_assert(sizeof(Aarch64_SCR_EL3) == 8); +static_assert(sizeof(SCR_EL3) == 8); -struct Aarch64_SPSR_EL2 { +struct SPSR_EL2 { enum Mode : u16 { EL0t = 0b0000, EL1t = 0b0100, @@ -385,14 +385,14 @@ struct Aarch64_SPSR_EL2 { int N : 1; int _reserved32 : 32 = 0; - static inline void write(Aarch64_SPSR_EL2 spsr_el2) + static inline void write(SPSR_EL2 spsr_el2) { asm("msr spsr_el2, %[value]" ::[value] "r"(spsr_el2)); } - static inline Aarch64_SPSR_EL2 read() + static inline SPSR_EL2 read() { - Aarch64_SPSR_EL2 spsr; + SPSR_EL2 spsr; asm("mrs %[value], spsr_el2" : [value] "=r"(spsr)); @@ -400,11 +400,11 @@ struct Aarch64_SPSR_EL2 { return spsr; } }; -static_assert(sizeof(Aarch64_SPSR_EL2) == 8); +static_assert(sizeof(SPSR_EL2) == 8); // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SPSR-EL3--Saved-Program-Status-Register--EL3- // Saved Program Status Register -struct Aarch64_SPSR_EL3 { +struct SPSR_EL3 { enum Mode : uint16_t { EL0t = 0b0000, EL1t = 0b0100, @@ -434,14 +434,14 @@ struct Aarch64_SPSR_EL3 { int N : 1; int _reserved32 : 32 = 0; - static inline void write(Aarch64_SPSR_EL3 spsr_el3) + static inline void write(SPSR_EL3 spsr_el3) { asm("msr spsr_el3, %[value]" ::[value] "r"(spsr_el3)); } - static inline Aarch64_SPSR_EL3 read() + static inline SPSR_EL3 read() { - Aarch64_SPSR_EL3 spsr; + SPSR_EL3 spsr; asm("mrs %[value], spsr_el3" : [value] "=r"(spsr)); @@ -449,18 +449,19 @@ struct Aarch64_SPSR_EL3 { return spsr; } }; -static_assert(sizeof(Aarch64_SPSR_EL3) == 8); +static_assert(sizeof(SPSR_EL3) == 8); // https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/MAIR-EL1--Memory-Attribute-Indirection-Register--EL1-?lang=en#fieldset_0-63_0 // Memory Attribute Indirection Register -struct Aarch64_MAIR_EL1 { +struct MAIR_EL1 { using AttributeEncoding = uint8_t; AttributeEncoding Attr[8]; - static inline void write(Aarch64_MAIR_EL1 mair_el1) + static inline void write(MAIR_EL1 mair_el1) { asm("msr mair_el1, %[value]" ::[value] "r"(mair_el1)); } }; -static_assert(sizeof(Aarch64_MAIR_EL1) == 8); +static_assert(sizeof(MAIR_EL1) == 8); + } diff --git a/Kernel/Prekernel/Arch/aarch64/PrekernelExceptions.cpp b/Kernel/Prekernel/Arch/aarch64/PrekernelExceptions.cpp index d7de7fccd7..d665d48fda 100644 --- a/Kernel/Prekernel/Arch/aarch64/PrekernelExceptions.cpp +++ b/Kernel/Prekernel/Arch/aarch64/PrekernelExceptions.cpp @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include @@ -18,16 +18,16 @@ namespace Prekernel { static void drop_to_el2() { - Aarch64_SCR_EL3 secure_configuration_register_el3 = {}; + Aarch64::SCR_EL3 secure_configuration_register_el3 = {}; secure_configuration_register_el3.ST = 1; // Don't trap access to Counter-timer Physical Secure registers secure_configuration_register_el3.RW = 1; // Lower level to use Aarch64 secure_configuration_register_el3.NS = 1; // Non-secure state secure_configuration_register_el3.HCE = 1; // Enable Hypervisor instructions at all levels - Aarch64_SCR_EL3::write(secure_configuration_register_el3); + Aarch64::SCR_EL3::write(secure_configuration_register_el3); - Aarch64_SPSR_EL3 saved_program_status_register_el3 = {}; + Aarch64::SPSR_EL3 saved_program_status_register_el3 = {}; // Mask (disable) all interrupts saved_program_status_register_el3.A = 1; @@ -36,21 +36,21 @@ static void drop_to_el2() saved_program_status_register_el3.D = 1; // Indicate EL1 as exception origin mode (so we go back there) - saved_program_status_register_el3.M = Aarch64_SPSR_EL3::Mode::EL2t; + saved_program_status_register_el3.M = Aarch64::SPSR_EL3::Mode::EL2t; // Set the register - Aarch64_SPSR_EL3::write(saved_program_status_register_el3); + Aarch64::SPSR_EL3::write(saved_program_status_register_el3); // This will jump into os_start() below enter_el2_from_el3(); } static void drop_to_el1() { - Aarch64_HCR_EL2 hypervisor_configuration_register_el2 = {}; + Aarch64::HCR_EL2 hypervisor_configuration_register_el2 = {}; hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode - Aarch64_HCR_EL2::write(hypervisor_configuration_register_el2); + Aarch64::HCR_EL2::write(hypervisor_configuration_register_el2); - Aarch64_SPSR_EL2 saved_program_status_register_el2 = {}; + Aarch64::SPSR_EL2 saved_program_status_register_el2 = {}; // Mask (disable) all interrupts saved_program_status_register_el2.A = 1; @@ -58,15 +58,15 @@ static void drop_to_el1() saved_program_status_register_el2.F = 1; // Indicate EL1 as exception origin mode (so we go back there) - saved_program_status_register_el2.M = Aarch64_SPSR_EL2::Mode::EL1t; + saved_program_status_register_el2.M = Aarch64::SPSR_EL2::Mode::EL1t; - Aarch64_SPSR_EL2::write(saved_program_status_register_el2); + Aarch64::SPSR_EL2::write(saved_program_status_register_el2); enter_el1_from_el2(); } static void set_up_el1() { - Aarch64_SCTLR_EL1 system_control_register_el1 = Aarch64_SCTLR_EL1::reset_value(); + Aarch64::SCTLR_EL1 system_control_register_el1 = Aarch64::SCTLR_EL1::reset_value(); system_control_register_el1.UCT = 1; // Don't trap access to CTR_EL0 system_control_register_el1.nTWE = 1; // Don't trap WFE instructions @@ -77,7 +77,7 @@ static void set_up_el1() system_control_register_el1.SA = 1; // Enable stack access alignment check for EL1 system_control_register_el1.A = 1; // Enable memory access alignment check - Aarch64_SCTLR_EL1::write(system_control_register_el1); + Aarch64::SCTLR_EL1::write(system_control_register_el1); } void drop_to_exception_level_1() diff --git a/Kernel/Prekernel/Arch/aarch64/PrekernelMMU.cpp b/Kernel/Prekernel/Arch/aarch64/PrekernelMMU.cpp index f3b7ef6d0f..b72f156e71 100644 --- a/Kernel/Prekernel/Arch/aarch64/PrekernelMMU.cpp +++ b/Kernel/Prekernel/Arch/aarch64/PrekernelMMU.cpp @@ -9,7 +9,7 @@ #include #include -#include +#include #include // Documentation here for Aarch64 Address Translations @@ -114,35 +114,35 @@ static void switch_to_page_table(u8* page_table) static void activate_mmu() { - Aarch64_MAIR_EL1 mair_el1 = {}; + Aarch64::MAIR_EL1 mair_el1 = {}; mair_el1.Attr[0] = 0xFF; // Normal memory mair_el1.Attr[1] = 0b00000100; // Device-nGnRE memory (non-cacheble) - Aarch64_MAIR_EL1::write(mair_el1); + Aarch64::MAIR_EL1::write(mair_el1); // Configure cacheability attributes for memory associated with translation table walks - Aarch64_TCR_EL1 tcr_el1 = {}; + Aarch64::TCR_EL1 tcr_el1 = {}; - tcr_el1.SH1 = Aarch64_TCR_EL1::InnerShareable; - tcr_el1.ORGN1 = Aarch64_TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable; - tcr_el1.IRGN1 = Aarch64_TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable; + tcr_el1.SH1 = Aarch64::TCR_EL1::InnerShareable; + tcr_el1.ORGN1 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable; + tcr_el1.IRGN1 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable; - tcr_el1.SH0 = Aarch64_TCR_EL1::InnerShareable; - tcr_el1.ORGN0 = Aarch64_TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable; - tcr_el1.IRGN0 = Aarch64_TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable; + tcr_el1.SH0 = Aarch64::TCR_EL1::InnerShareable; + tcr_el1.ORGN0 = Aarch64::TCR_EL1::NormalMemory_Outer_WriteBack_ReadAllocate_WriteAllocateCacheable; + tcr_el1.IRGN0 = Aarch64::TCR_EL1::NormalMemory_Inner_WriteBack_ReadAllocate_WriteAllocateCacheable; - tcr_el1.TG1 = Aarch64_TCR_EL1::TG1GranuleSize::Size_4KB; - tcr_el1.TG0 = Aarch64_TCR_EL1::TG0GranuleSize::Size_4KB; + tcr_el1.TG1 = Aarch64::TCR_EL1::TG1GranuleSize::Size_4KB; + tcr_el1.TG0 = Aarch64::TCR_EL1::TG0GranuleSize::Size_4KB; // Auto detect the Intermediate Physical Address Size - Aarch64_ID_AA64MMFR0_EL1 feature_register = Aarch64_ID_AA64MMFR0_EL1::read(); + Aarch64::ID_AA64MMFR0_EL1 feature_register = Aarch64::ID_AA64MMFR0_EL1::read(); tcr_el1.IPS = feature_register.PARange; - Aarch64_TCR_EL1::write(tcr_el1); + Aarch64::TCR_EL1::write(tcr_el1); // Enable MMU in the system control register - Aarch64_SCTLR_EL1 sctlr_el1 = Aarch64_SCTLR_EL1::read(); + Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::read(); sctlr_el1.M = 1; //Enable MMU - Aarch64_SCTLR_EL1::write(sctlr_el1); + Aarch64::SCTLR_EL1::write(sctlr_el1); flush(); }