From 3623e359782d65aa5b460c15a8bfe1dbb0bc057f Mon Sep 17 00:00:00 2001
From: Andreas Kling <awesomekling@gmail.com>
Date: Tue, 24 Dec 2019 22:45:27 +0100
Subject: [PATCH] Kernel: Oops, actually enable CR4.PGE (page table global bit)

Turns out we were setting the wrong bit here. Now we will actually keep
kernel memory mappings in the TLB across context switches.
---
 Kernel/VM/MemoryManager.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Kernel/VM/MemoryManager.cpp b/Kernel/VM/MemoryManager.cpp
index d69eb86f66..0ebe60bfea 100644
--- a/Kernel/VM/MemoryManager.cpp
+++ b/Kernel/VM/MemoryManager.cpp
@@ -168,7 +168,7 @@ void MemoryManager::initialize_paging()
     // Turn on CR4.PGE so the CPU will respect the G bit in page tables.
     asm volatile(
         "mov %cr4, %eax\n"
-        "orl $0x10, %eax\n"
+        "orl $0x40, %eax\n"
         "mov %eax, %cr4\n");
 
     asm volatile("movl %%eax, %%cr3" ::"a"(kernel_page_directory().cr3()));