RGBCube/serenity
1
Fork 0
mirror of https://github.com/RGBCube/serenity synced 2025-07-26 06:17:34 +00:00
Code Issues Activity Actions

Kernel: Enable SMAP protection on IRQ and exception entry

Browse source 
It would be nice to do this in the assembly code, but we have to check
if the feature is available before doing a CLAC, so I've put this in
the C++ code for now.
This commit is contained in:
Andreas Kling 2020-01-08 07:27:37 +01:00
parent fe9680f0a4
commit 372f9e9a11
2 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Kernel/Arch/i386/CPU.cpp
View file

@ -189,18 +189,21 @@ void handle_crash(RegisterDump& regs, const char* description, int signal)
EH_ENTRY_NO_CODE(6, illegal_instruction);
void illegal_instruction_handler(RegisterDump regs)
{
clac();
handle_crash(regs, "Illegal instruction", SIGILL);
}
EH_ENTRY_NO_CODE(0, divide_error);
void divide_error_handler(RegisterDump regs)
{
clac();
handle_crash(regs, "Divide error", SIGFPE);
}
EH_ENTRY(13, general_protection_fault);
void general_protection_fault_handler(RegisterDump regs)
{
clac();
handle_crash(regs, "General protection fault", SIGSEGV);
}
@ -217,6 +220,7 @@ void fpu_exception_handler(RegisterDump)
EH_ENTRY(14, page_fault);
void page_fault_handler(RegisterDump regs)
{
clac();
ASSERT(current);
u32 fault_address;
@ -491,6 +495,7 @@ void load_task_register(u16 selector)
void handle_irq(RegisterDump regs)
{
clac();
ASSERT(regs.isr_number >= 0x50 && regs.isr_number <= 0x5f);
u8 irq = (u8)(regs.isr_number - 0x50);
if (s_irq_handler[irq])