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Kernel/USB: Move UHCI related structures to subdirectory

Browse source 
The number of UHCI related files is starting to expand to the point
where it's best if we move this into their own subdirectory. It'll
also make it easier to manage when we decide to add some more
controller types (whenever that may be)
This commit is contained in:
Jesse Buhagiar 2021-08-13 16:10:43 +10:00 • committed by Andreas Kling
parent 43392c567e
commit 4abf399a74
8 changed files with 9 additions and 9 deletions
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738
Kernel/Bus/USB/UHCI/UHCIController.cpp Normal file
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/*
* Copyright (c) 2020-2021, Andreas Kling <kling@serenityos.org>
* Copyright (c) 2020, Jesse Buhagiar <jooster669@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <AK/Platform.h>
#include <Kernel/Bus/USB/UHCI/UHCIController.h>
#include <Kernel/Bus/USB/USBRequest.h>
#include <Kernel/CommandLine.h>
#include <Kernel/Debug.h>
#include <Kernel/Memory/AnonymousVMObject.h>
#include <Kernel/Memory/MemoryManager.h>
#include <Kernel/Process.h>
#include <Kernel/Sections.h>
#include <Kernel/StdLib.h>
#include <Kernel/Time/TimeManagement.h>
static constexpr u8 MAXIMUM_NUMBER_OF_TDS = 128; // Upper pool limit. This consumes the second page we have allocated
static constexpr u8 MAXIMUM_NUMBER_OF_QHS = 64;
static constexpr u8 RETRY_COUNTER_RELOAD = 3;
namespace Kernel::USB {
static constexpr u16 UHCI_USBCMD_RUN = 0x0001;
static constexpr u16 UHCI_USBCMD_HOST_CONTROLLER_RESET = 0x0002;
static constexpr u16 UHCI_USBCMD_GLOBAL_RESET = 0x0004;
static constexpr u16 UHCI_USBCMD_ENTER_GLOBAL_SUSPEND_MODE = 0x0008;
static constexpr u16 UHCI_USBCMD_FORCE_GLOBAL_RESUME = 0x0010;
static constexpr u16 UHCI_USBCMD_SOFTWARE_DEBUG = 0x0020;
static constexpr u16 UHCI_USBCMD_CONFIGURE_FLAG = 0x0040;
static constexpr u16 UHCI_USBCMD_MAX_PACKET = 0x0080;
static constexpr u16 UHCI_USBSTS_HOST_CONTROLLER_HALTED = 0x0020;
static constexpr u16 UHCI_USBSTS_HOST_CONTROLLER_PROCESS_ERROR = 0x0010;
static constexpr u16 UHCI_USBSTS_PCI_BUS_ERROR = 0x0008;
static constexpr u16 UHCI_USBSTS_RESUME_RECEIVED = 0x0004;
static constexpr u16 UHCI_USBSTS_USB_ERROR_INTERRUPT = 0x0002;
static constexpr u16 UHCI_USBSTS_USB_INTERRUPT = 0x0001;
static constexpr u8 UHCI_USBINTR_TIMEOUT_CRC_ENABLE = 0x01;
static constexpr u8 UHCI_USBINTR_RESUME_INTR_ENABLE = 0x02;
static constexpr u8 UHCI_USBINTR_IOC_ENABLE = 0x04;
static constexpr u8 UHCI_USBINTR_SHORT_PACKET_INTR_ENABLE = 0x08;
static constexpr u16 UHCI_FRAMELIST_FRAME_COUNT = 1024; // Each entry is 4 bytes in our allocated page
static constexpr u16 UHCI_FRAMELIST_FRAME_INVALID = 0x0001;
// Port stuff
static constexpr u8 UHCI_ROOT_PORT_COUNT = 2;
static constexpr u16 UHCI_PORTSC_CURRRENT_CONNECT_STATUS = 0x0001;
static constexpr u16 UHCI_PORTSC_CONNECT_STATUS_CHANGED = 0x0002;
static constexpr u16 UHCI_PORTSC_PORT_ENABLED = 0x0004;
static constexpr u16 UHCI_PORTSC_PORT_ENABLE_CHANGED = 0x0008;
static constexpr u16 UHCI_PORTSC_LINE_STATUS = 0x0030;
static constexpr u16 UHCI_PORTSC_RESUME_DETECT = 0x40;
static constexpr u16 UHCI_PORTSC_LOW_SPEED_DEVICE = 0x0100;
static constexpr u16 UHCI_PORTSC_PORT_RESET = 0x0200;
static constexpr u16 UHCI_PORTSC_SUSPEND = 0x1000;
static constexpr u16 UCHI_PORTSC_NON_WRITE_CLEAR_BIT_MASK = 0x1FF5; // This is used to mask out the Write Clear bits making sure we don't accidentally clear them.
// *BSD and a few other drivers seem to use this number
static constexpr u8 UHCI_NUMBER_OF_ISOCHRONOUS_TDS = 128;
static constexpr u16 UHCI_NUMBER_OF_FRAMES = 1024;
KResultOr<NonnullRefPtr<UHCIController>> UHCIController::try_to_initialize(PCI::Address address)
{
// NOTE: This assumes that address is pointing to a valid UHCI controller.
auto controller = adopt_ref_if_nonnull(new (nothrow) UHCIController(address));
if (!controller)
return ENOMEM;
auto init_result = controller->initialize();
if (init_result.is_error())
return init_result;
return controller.release_nonnull();
}
KResult UHCIController::initialize()
{
dmesgln("UHCI: Controller found {} @ {}", PCI::get_id(pci_address()), pci_address());
dmesgln("UHCI: I/O base {}", m_io_base);
dmesgln("UHCI: Interrupt line: {}", PCI::get_interrupt_line(pci_address()));
spawn_port_proc();
auto reset_result = reset();
if (reset_result.is_error())
return reset_result;
auto start_result = start();
return start_result;
}
UNMAP_AFTER_INIT UHCIController::UHCIController(PCI::Address address)
: PCI::Device(address)
, m_io_base(PCI::get_BAR4(pci_address()) & ~1)
{
}
UNMAP_AFTER_INIT UHCIController::~UHCIController()
{
}
KResult UHCIController::reset()
{
if (auto stop_result = stop(); stop_result.is_error())
return stop_result;
write_usbcmd(UHCI_USBCMD_HOST_CONTROLLER_RESET);
// FIXME: Timeout
for (;;) {
if (read_usbcmd() & UHCI_USBCMD_HOST_CONTROLLER_RESET)
continue;
break;
}
// Let's allocate the physical page for the Frame List (which is 4KiB aligned)
auto maybe_framelist_vmobj = Memory::AnonymousVMObject::try_create_physically_contiguous_with_size(PAGE_SIZE);
if (maybe_framelist_vmobj.is_error())
return maybe_framelist_vmobj.error();
m_framelist = MM.allocate_kernel_region_with_vmobject(maybe_framelist_vmobj.release_value(), PAGE_SIZE, "UHCI Framelist", Memory::Region::Access::Write);
dbgln("UHCI: Allocated framelist at physical address {}", m_framelist->physical_page(0)->paddr());
dbgln("UHCI: Framelist is at virtual address {}", m_framelist->vaddr());
write_sofmod(64); // 1mS frame time
if (auto result = create_structures(); result.is_error())
return result;
setup_schedule();
write_flbaseadd(m_framelist->physical_page(0)->paddr().get()); // Frame list (physical) address
write_frnum(0); // Set the initial frame number
// FIXME: Work out why interrupts lock up the entire system....
// Disable UHCI Controller from raising an IRQ
write_usbintr(0);
dbgln("UHCI: Reset completed");
return KSuccess;
}
UNMAP_AFTER_INIT KResult UHCIController::create_structures()
{
// Let's allocate memory for both the QH and TD pools
// First the QH pool and all of the Interrupt QH's
auto maybe_qh_pool_vmobject = Memory::AnonymousVMObject::try_create_physically_contiguous_with_size(2 * PAGE_SIZE);
if (maybe_qh_pool_vmobject.is_error())
return maybe_qh_pool_vmobject.error();
m_qh_pool = MM.allocate_kernel_region_with_vmobject(maybe_qh_pool_vmobject.release_value(), 2 * PAGE_SIZE, "UHCI Queue Head Pool", Memory::Region::Access::Write);
memset(m_qh_pool->vaddr().as_ptr(), 0, 2 * PAGE_SIZE); // Zero out both pages
// Let's populate our free qh list (so we have some we can allocate later on)
m_free_qh_pool.resize(MAXIMUM_NUMBER_OF_TDS);
for (size_t i = 0; i < m_free_qh_pool.size(); i++) {
auto placement_addr = reinterpret_cast<void*>(m_qh_pool->vaddr().get() + (i * sizeof(QueueHead)));
auto paddr = static_cast<u32>(m_qh_pool->physical_page(0)->paddr().get() + (i * sizeof(QueueHead)));
m_free_qh_pool.at(i) = new (placement_addr) QueueHead(paddr);
}
// Create the Full Speed, Low Speed Control and Bulk Queue Heads
m_interrupt_transfer_queue = allocate_queue_head();
m_lowspeed_control_qh = allocate_queue_head();
m_fullspeed_control_qh = allocate_queue_head();
m_bulk_qh = allocate_queue_head();
m_dummy_qh = allocate_queue_head();
// Now the Transfer Descriptor pool
auto maybe_td_pool_vmobject = Memory::AnonymousVMObject::try_create_physically_contiguous_with_size(2 * PAGE_SIZE);
if (maybe_td_pool_vmobject.is_error())
return maybe_td_pool_vmobject.error();
m_td_pool = MM.allocate_kernel_region_with_vmobject(maybe_td_pool_vmobject.release_value(), 2 * PAGE_SIZE, "UHCI Transfer Descriptor Pool", Memory::Region::Access::Write);
memset(m_td_pool->vaddr().as_ptr(), 0, 2 * PAGE_SIZE);
// Set up the Isochronous Transfer Descriptor list
m_iso_td_list.resize(UHCI_NUMBER_OF_ISOCHRONOUS_TDS);
for (size_t i = 0; i < m_iso_td_list.size(); i++) {
auto placement_addr = reinterpret_cast<void*>(m_td_pool->vaddr().get() + (i * sizeof(Kernel::USB::TransferDescriptor)));
auto paddr = static_cast<u32>(m_td_pool->physical_page(0)->paddr().get() + (i * sizeof(Kernel::USB::TransferDescriptor)));
// Place a new Transfer Descriptor with a 1:1 in our region
// The pointer returned by `new()` lines up exactly with the value
// that we store in `paddr`, meaning our member functions directly
// access the raw descriptor (that we later send to the controller)
m_iso_td_list.at(i) = new (placement_addr) Kernel::USB::TransferDescriptor(paddr);
auto transfer_descriptor = m_iso_td_list.at(i);
transfer_descriptor->set_in_use(true); // Isochronous transfers are ALWAYS marked as in use (in case we somehow get allocated one...)
transfer_descriptor->set_isochronous();
transfer_descriptor->link_queue_head(m_interrupt_transfer_queue->paddr());
if constexpr (UHCI_VERBOSE_DEBUG)
transfer_descriptor->print();
}
m_free_td_pool.resize(MAXIMUM_NUMBER_OF_TDS);
for (size_t i = 0; i < m_free_td_pool.size(); i++) {
auto placement_addr = reinterpret_cast<void*>(m_td_pool->vaddr().offset(PAGE_SIZE).get() + (i * sizeof(Kernel::USB::TransferDescriptor)));
auto paddr = static_cast<u32>(m_td_pool->physical_page(1)->paddr().get() + (i * sizeof(Kernel::USB::TransferDescriptor)));
// Place a new Transfer Descriptor with a 1:1 in our region
// The pointer returned by `new()` lines up exactly with the value
// that we store in `paddr`, meaning our member functions directly
// access the raw descriptor (that we later send to the controller)
m_free_td_pool.at(i) = new (placement_addr) Kernel::USB::TransferDescriptor(paddr);
if constexpr (UHCI_VERBOSE_DEBUG) {
auto transfer_descriptor = m_free_td_pool.at(i);
transfer_descriptor->print();
}
}
if constexpr (UHCI_DEBUG) {
dbgln("UHCI: Pool information:");
dbgln(" qh_pool: {}, length: {}", PhysicalAddress(m_qh_pool->physical_page(0)->paddr()), m_qh_pool->range().size());
dbgln(" td_pool: {}, length: {}", PhysicalAddress(m_td_pool->physical_page(0)->paddr()), m_td_pool->range().size());
}
return KSuccess;
}
UNMAP_AFTER_INIT void UHCIController::setup_schedule()
{
//
// https://github.com/alkber/minix3-usbsubsystem/blob/master/usb/uhci-hcd.c
//
// This lad probably has the best explanation as to how this is actually done. I'll try and
// explain it here to so that there's no need for anyone to go hunting for this shit again, because
// the USB spec and Intel explain next to nothing.
// According to the USB spec (and the UHCI datasheet), 90% of the bandwidth should be used for
// Isochronous and """Interrupt""" related transfers, with the rest being used for control and bulk
// transfers.
// That is, most of the time, the schedule is going to be executing either an Isochronous transfer
// in our framelist, or an Interrupt transfer. The allocation in `create_structures` reflects this.
//
// Each frame has it's own Isochronous transfer Transfer Descriptor(s) that point to each other
// horizontally in the list. The end of these transfers then point to the Interrupt Queue Headers,
// in which we can attach Transfer Descriptors (related to Interrupt Transfers). These are attached
// to the Queue Head _vertically_. We need to ensure that these are executed every 8ms, so they are inserted
// at different points in the schedule (TODO: How do we do this?!?!). After the Interrupt Transfer Queue Heads,
// we attach the Control Queue Heads. We need two in total, one for Low Speed devices, and one for Full Speed
// USB devices. Finally, we attach the Bulk Transfer Queue Head.
// Not specified in the datasheet, however, is another Queue Head with an "inactive" Transfer Descriptor. This
// is to circumvent a bug in the silicon of the PIIX4's UHCI controller.
// https://github.com/openbsd/src/blob/master/sys/dev/usb/uhci.c#L390
//
m_interrupt_transfer_queue->link_next_queue_head(m_lowspeed_control_qh);
m_interrupt_transfer_queue->terminate_element_link_ptr();
m_lowspeed_control_qh->link_next_queue_head(m_fullspeed_control_qh);
m_lowspeed_control_qh->terminate_element_link_ptr();
m_fullspeed_control_qh->link_next_queue_head(m_bulk_qh);
m_fullspeed_control_qh->terminate_element_link_ptr();
m_bulk_qh->link_next_queue_head(m_dummy_qh);
m_bulk_qh->terminate_element_link_ptr();
auto piix4_td_hack = allocate_transfer_descriptor();
piix4_td_hack->terminate();
piix4_td_hack->set_max_len(0x7ff); // Null data packet
piix4_td_hack->set_device_address(0x7f);
piix4_td_hack->set_packet_id(PacketID::IN);
m_dummy_qh->terminate_with_stray_descriptor(piix4_td_hack);
m_dummy_qh->terminate_element_link_ptr();
u32* framelist = reinterpret_cast<u32*>(m_framelist->vaddr().as_ptr());
for (int frame = 0; frame < UHCI_NUMBER_OF_FRAMES; frame++) {
// Each frame pointer points to iso_td % NUM_ISO_TDS
framelist[frame] = m_iso_td_list.at(frame % UHCI_NUMBER_OF_ISOCHRONOUS_TDS)->paddr();
}
m_interrupt_transfer_queue->print();
m_lowspeed_control_qh->print();
m_fullspeed_control_qh->print();
m_bulk_qh->print();
m_dummy_qh->print();
}
QueueHead* UHCIController::allocate_queue_head() const
{
for (QueueHead* queue_head : m_free_qh_pool) {
if (!queue_head->in_use()) {
queue_head->set_in_use(true);
dbgln_if(UHCI_DEBUG, "UHCI: Allocated a new Queue Head! Located @ {} ({})", VirtualAddress(queue_head), PhysicalAddress(queue_head->paddr()));
return queue_head;
}
}
return nullptr; // Huh!? We're outta queue heads!
}
TransferDescriptor* UHCIController::allocate_transfer_descriptor() const
{
for (TransferDescriptor* transfer_descriptor : m_free_td_pool) {
if (!transfer_descriptor->in_use()) {
transfer_descriptor->set_in_use(true);
dbgln_if(UHCI_DEBUG, "UHCI: Allocated a new Transfer Descriptor! Located @ {} ({})", VirtualAddress(transfer_descriptor), PhysicalAddress(transfer_descriptor->paddr()));
return transfer_descriptor;
}
}
return nullptr; // Huh?! We're outta TDs!!
}
KResult UHCIController::stop()
{
write_usbcmd(read_usbcmd() & ~UHCI_USBCMD_RUN);
// FIXME: Timeout
for (;;) {
if (read_usbsts() & UHCI_USBSTS_HOST_CONTROLLER_HALTED)
break;
}
return KSuccess;
}
KResult UHCIController::start()
{
write_usbcmd(read_usbcmd() | UHCI_USBCMD_RUN);
// FIXME: Timeout
for (;;) {
if (!(read_usbsts() & UHCI_USBSTS_HOST_CONTROLLER_HALTED))
break;
}
dbgln("UHCI: Started");
auto root_hub_or_error = UHCIRootHub::try_create(*this);
if (root_hub_or_error.is_error())
return root_hub_or_error.error();
m_root_hub = root_hub_or_error.release_value();
auto result = m_root_hub->setup({});
if (result.is_error())
return result;
return KSuccess;
}
TransferDescriptor* UHCIController::create_transfer_descriptor(Pipe& pipe, PacketID direction, size_t data_len)
{
TransferDescriptor* td = allocate_transfer_descriptor();
if (td == nullptr) {
return nullptr;
}
u16 max_len = (data_len > 0) ? (data_len - 1) : 0x7ff;
VERIFY(max_len <= 0x4FF || max_len == 0x7FF); // According to the datasheet, anything in the range of 0x500 to 0x7FE are illegal
td->set_token((max_len << TD_TOKEN_MAXLEN_SHIFT) | ((pipe.data_toggle() ? 1 : 0) << TD_TOKEN_DATA_TOGGLE_SHIFT) | (pipe.endpoint_address() << TD_TOKEN_ENDPOINT_SHIFT) | (pipe.device_address() << TD_TOKEN_DEVICE_ADDR_SHIFT) | (static_cast<u8>(direction)));
pipe.set_toggle(!pipe.data_toggle());
if (pipe.type() == Pipe::Type::Isochronous) {
td->set_isochronous();
} else {
if (direction == PacketID::IN) {
td->set_short_packet_detect();
}
}
// Set low-speed bit if the device connected to port is a low=speed device (probably unlikely...)
if (pipe.device_speed() == Pipe::DeviceSpeed::LowSpeed) {
td->set_lowspeed();
}
td->set_active();
td->set_error_retry_counter(RETRY_COUNTER_RELOAD);
return td;
}
KResult UHCIController::create_chain(Pipe& pipe, PacketID direction, Ptr32<u8>& buffer_address, size_t max_size, size_t transfer_size, TransferDescriptor** td_chain, TransferDescriptor** last_td)
{
// We need to create `n` transfer descriptors based on the max
// size of each transfer (which we've learned from the device already by reading
// its device descriptor, or 8 bytes). Each TD then has its buffer pointer
// set to the initial buffer address + (max_size * index), where index is
// the ID of the TD in the chain.
size_t byte_count = 0;
TransferDescriptor* current_td = nullptr;
TransferDescriptor* prev_td = nullptr;
TransferDescriptor* first_td = nullptr;
// Keep creating transfer descriptors while we still have some data
while (byte_count < transfer_size) {
size_t packet_size = transfer_size - byte_count;
if (packet_size > max_size) {
packet_size = max_size;
}
current_td = create_transfer_descriptor(pipe, direction, packet_size);
if (current_td == nullptr) {
free_descriptor_chain(first_td);
return ENOMEM;
}
if (Checked<FlatPtr>::addition_would_overflow(reinterpret_cast<FlatPtr>(&*buffer_address), byte_count))
return EOVERFLOW;
auto buffer_pointer = Ptr32<u8>(buffer_address + byte_count);
current_td->set_buffer_address(buffer_pointer);
byte_count += packet_size;
if (prev_td != nullptr)
prev_td->insert_next_transfer_descriptor(current_td);
else
first_td = current_td;
prev_td = current_td;
}
*last_td = current_td;
*td_chain = first_td;
return KSuccess;
}
void UHCIController::free_descriptor_chain(TransferDescriptor* first_descriptor)
{
TransferDescriptor* descriptor = first_descriptor;
while (descriptor) {
descriptor->free();
descriptor = descriptor->next_td();
}
}
KResultOr<size_t> UHCIController::submit_control_transfer(Transfer& transfer)
{
Pipe& pipe = transfer.pipe(); // Short circuit the pipe related to this transfer
bool direction_in = (transfer.request().request_type & USB_REQUEST_TRANSFER_DIRECTION_DEVICE_TO_HOST) == USB_REQUEST_TRANSFER_DIRECTION_DEVICE_TO_HOST;
dbgln_if(UHCI_DEBUG, "UHCI: Received control transfer for address {}. Root Hub is at address {}.", pipe.device_address(), m_root_hub->device_address());
// Short-circuit the root hub.
if (pipe.device_address() == m_root_hub->device_address())
return m_root_hub->handle_control_transfer(transfer);
TransferDescriptor* setup_td = create_transfer_descriptor(pipe, PacketID::SETUP, sizeof(USBRequestData));
if (!setup_td)
return ENOMEM;
setup_td->set_buffer_address(transfer.buffer_physical().as_ptr());
// Create a new descriptor chain
TransferDescriptor* last_data_descriptor;
TransferDescriptor* data_descriptor_chain;
auto buffer_address = Ptr32<u8>(transfer.buffer_physical().as_ptr() + sizeof(USBRequestData));
if (auto result = create_chain(pipe, direction_in ? PacketID::IN : PacketID::OUT, buffer_address, pipe.max_packet_size(), transfer.transfer_data_size(), &data_descriptor_chain, &last_data_descriptor); result.is_error())
return result;
// Status TD always has toggle set to 1
pipe.set_toggle(true);
TransferDescriptor* status_td = create_transfer_descriptor(pipe, direction_in ? PacketID::OUT : PacketID::IN, 0);
if (!status_td) {
free_descriptor_chain(data_descriptor_chain);
return ENOMEM;
}
status_td->terminate();
// Link transfers together
if (data_descriptor_chain) {
setup_td->insert_next_transfer_descriptor(data_descriptor_chain);
last_data_descriptor->insert_next_transfer_descriptor(status_td);
} else {
setup_td->insert_next_transfer_descriptor(status_td);
}
// Cool, everything should be chained together now! Let's print it out
if constexpr (UHCI_VERBOSE_DEBUG) {
dbgln("Setup TD");
setup_td->print();
if (data_descriptor_chain) {
dbgln("Data TD");
data_descriptor_chain->print();
}
dbgln("Status TD");
status_td->print();
}
QueueHead* transfer_queue = allocate_queue_head();
if (!transfer_queue) {
free_descriptor_chain(data_descriptor_chain);
return 0;
}
transfer_queue->attach_transfer_descriptor_chain(setup_td);
transfer_queue->set_transfer(&transfer);
m_fullspeed_control_qh->attach_transfer_queue(*transfer_queue);
size_t transfer_size = 0;
while (!transfer.complete())
transfer_size = poll_transfer_queue(*transfer_queue);
free_descriptor_chain(transfer_queue->get_first_td());
transfer_queue->free();
return transfer_size;
}
size_t UHCIController::poll_transfer_queue(QueueHead& transfer_queue)
{
Transfer* transfer = transfer_queue.transfer();
TransferDescriptor* descriptor = transfer_queue.get_first_td();
bool transfer_still_in_progress = false;
size_t transfer_size = 0;
while (descriptor) {
u32 status = descriptor->status();
if (status & TransferDescriptor::StatusBits::Active) {
transfer_still_in_progress = true;
break;
}
if (status & TransferDescriptor::StatusBits::ErrorMask) {
transfer->set_complete();
transfer->set_error_occurred();
dbgln_if(UHCI_DEBUG, "UHCIController: Transfer failed! Reason: {:08x}", status);
return 0;
}
transfer_size += descriptor->actual_packet_length();
descriptor = descriptor->next_td();
}
if (!transfer_still_in_progress)
transfer->set_complete();
return transfer_size;
}
void UHCIController::spawn_port_proc()
{
RefPtr<Thread> usb_hotplug_thread;
Process::create_kernel_process(usb_hotplug_thread, "UHCIHotplug", [&] {
for (;;) {
if (m_root_hub)
m_root_hub->check_for_port_updates();
(void)Thread::current()->sleep(Time::from_seconds(1));
}
});
}
bool UHCIController::handle_irq(const RegisterState&)
{
u32 status = read_usbsts();
// Shared IRQ. Not ours!
if (!status)
return false;
if constexpr (UHCI_DEBUG) {
dbgln("UHCI: Interrupt happened!");
dbgln("Value of USBSTS: {:#04x}", read_usbsts());
}
// Write back USBSTS to clear bits
write_usbsts(status);
return true;
}
void UHCIController::get_port_status(Badge<UHCIRootHub>, u8 port, HubStatus& hub_port_status)
{
// The check is done by UHCIRootHub.
VERIFY(port < NUMBER_OF_ROOT_PORTS);
u16 status = port == 0 ? read_portsc1() : read_portsc2();
if (status & UHCI_PORTSC_CURRRENT_CONNECT_STATUS)
hub_port_status.status |= PORT_STATUS_CURRENT_CONNECT_STATUS;
if (status & UHCI_PORTSC_CONNECT_STATUS_CHANGED)
hub_port_status.change |= PORT_STATUS_CONNECT_STATUS_CHANGED;
if (status & UHCI_PORTSC_PORT_ENABLED)
hub_port_status.status |= PORT_STATUS_PORT_ENABLED;
if (status & UHCI_PORTSC_PORT_ENABLE_CHANGED)
hub_port_status.change |= PORT_STATUS_PORT_ENABLED_CHANGED;
if (status & UHCI_PORTSC_LOW_SPEED_DEVICE)
hub_port_status.status |= PORT_STATUS_LOW_SPEED_DEVICE_ATTACHED;
if (status & UHCI_PORTSC_PORT_RESET)
hub_port_status.status |= PORT_STATUS_RESET;
if (m_port_reset_change_statuses & (1 << port))
hub_port_status.change |= PORT_STATUS_RESET_CHANGED;
if (status & UHCI_PORTSC_SUSPEND)
hub_port_status.status |= PORT_STATUS_SUSPEND;
if (m_port_suspend_change_statuses & (1 << port))
hub_port_status.change |= PORT_STATUS_SUSPEND_CHANGED;
// UHCI ports are always powered.
hub_port_status.status |= PORT_STATUS_PORT_POWER;
dbgln_if(UHCI_DEBUG, "UHCI: get_port_status status=0x{:04x} change=0x{:04x}", hub_port_status.status, hub_port_status.change);
}
void UHCIController::reset_port(u8 port)
{
// We still have to reset the port manually because UHCI does not automatically enable the port after reset.
// Additionally, the USB 2.0 specification says the SetPortFeature(PORT_ENABLE) request is not specified and that the _ideal_ behaviour is to return a Request Error.
// Source: USB 2.0 Specification Section 11.24.2.7.1.2
// This means the hub code cannot rely on using it.
// The check is done by UHCIRootHub and set_port_feature.
VERIFY(port < NUMBER_OF_ROOT_PORTS);
u16 port_data = port == 0 ? read_portsc1() : read_portsc2();
port_data &= UCHI_PORTSC_NON_WRITE_CLEAR_BIT_MASK;
port_data |= UHCI_PORTSC_PORT_RESET;
if (port == 0)
write_portsc1(port_data);
else
write_portsc2(port_data);
// Wait at least 50 ms for the port to reset.
// This is T DRSTR in the USB 2.0 Specification Page 186 Table 7-13.
constexpr u16 reset_delay = 50 * 1000;
IO::delay(reset_delay);
port_data &= ~UHCI_PORTSC_PORT_RESET;
if (port == 0)
write_portsc1(port_data);
else
write_portsc2(port_data);
// Wait 10 ms for the port to recover.
// This is T RSTRCY in the USB 2.0 Specification Page 188 Table 7-14.
constexpr u16 reset_recovery_delay = 10 * 1000;
IO::delay(reset_recovery_delay);
port_data = port == 0 ? read_portsc1() : read_portsc2();
port_data |= UHCI_PORTSC_PORT_ENABLED;
if (port == 0)
write_portsc1(port_data);
else
write_portsc2(port_data);
dbgln_if(UHCI_DEBUG, "UHCI: Port should be enabled now: {:#04x}", port == 0 ? read_portsc1() : read_portsc2());
m_port_reset_change_statuses |= (1 << port);
}
KResult UHCIController::set_port_feature(Badge<UHCIRootHub>, u8 port, HubFeatureSelector feature_selector)
{
// The check is done by UHCIRootHub.
VERIFY(port < NUMBER_OF_ROOT_PORTS);
dbgln_if(UHCI_DEBUG, "UHCI: set_port_feature: port={} feature_selector={}", port, (u8)feature_selector);
switch (feature_selector) {
case HubFeatureSelector::PORT_POWER:
// Ignore the request. UHCI ports are always powered.
break;
case HubFeatureSelector::PORT_RESET:
reset_port(port);
break;
case HubFeatureSelector::PORT_SUSPEND: {
u16 port_data = port == 0 ? read_portsc1() : read_portsc2();
port_data &= UCHI_PORTSC_NON_WRITE_CLEAR_BIT_MASK;
port_data |= UHCI_PORTSC_SUSPEND;
if (port == 0)
write_portsc1(port_data);
else
write_portsc2(port_data);
m_port_suspend_change_statuses |= (1 << port);
break;
}
default:
dbgln("UHCI: Unknown feature selector in set_port_feature: {}", (u8)feature_selector);
return EINVAL;
}
return KSuccess;
}
KResult UHCIController::clear_port_feature(Badge<UHCIRootHub>, u8 port, HubFeatureSelector feature_selector)
{
// The check is done by UHCIRootHub.
VERIFY(port < NUMBER_OF_ROOT_PORTS);
dbgln_if(UHCI_DEBUG, "UHCI: clear_port_feature: port={} feature_selector={}", port, (u8)feature_selector);
u16 port_data = port == 0 ? read_portsc1() : read_portsc2();
port_data &= UCHI_PORTSC_NON_WRITE_CLEAR_BIT_MASK;
switch (feature_selector) {
case HubFeatureSelector::PORT_ENABLE:
port_data &= ~UHCI_PORTSC_PORT_ENABLED;
break;
case HubFeatureSelector::PORT_SUSPEND:
port_data &= ~UHCI_PORTSC_SUSPEND;
break;
case HubFeatureSelector::PORT_POWER:
// Ignore the request. UHCI ports are always powered.
break;
case HubFeatureSelector::C_PORT_CONNECTION:
// This field is Write Clear.
port_data |= UHCI_PORTSC_CONNECT_STATUS_CHANGED;
break;
case HubFeatureSelector::C_PORT_RESET:
m_port_reset_change_statuses &= ~(1 << port);
break;
case HubFeatureSelector::C_PORT_ENABLE:
// This field is Write Clear.
port_data |= UHCI_PORTSC_PORT_ENABLE_CHANGED;
break;
case HubFeatureSelector::C_PORT_SUSPEND:
m_port_suspend_change_statuses &= ~(1 << port);
break;
default:
dbgln("UHCI: Unknown feature selector in clear_port_feature: {}", (u8)feature_selector);
return EINVAL;
}
dbgln_if(UHCI_DEBUG, "UHCI: clear_port_feature: writing 0x{:04x} to portsc{}.", port_data, port + 1);
if (port == 0)
write_portsc1(port_data);
else
write_portsc2(port_data);
return KSuccess;
}
}

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/*
* Copyright (c) 2020, Andreas Kling <kling@serenityos.org>
* Copyright (c) 2020-2021, Jesse Buhagiar <jooster669@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/Platform.h>
#include <AK/NonnullOwnPtr.h>
#include <Kernel/Bus/PCI/Device.h>
#include <Kernel/Bus/USB/UHCI/UHCIDescriptorTypes.h>
#include <Kernel/Bus/USB/UHCI/UHCIRootHub.h>
#include <Kernel/Bus/USB/USBController.h>
#include <Kernel/IO.h>
#include <Kernel/Memory/AnonymousVMObject.h>
#include <Kernel/Process.h>
#include <Kernel/Time/TimeManagement.h>
namespace Kernel::USB {
class UHCIController final
: public USBController
, public PCI::Device {
public:
static constexpr u8 NUMBER_OF_ROOT_PORTS = 2;
static KResultOr<NonnullRefPtr<UHCIController>> try_to_initialize(PCI::Address address);
virtual ~UHCIController() override;
virtual StringView purpose() const override { return "UHCI"; }
virtual KResult initialize() override;
virtual KResult reset() override;
virtual KResult stop() override;
virtual KResult start() override;
void spawn_port_proc();
void do_debug_transfer();
virtual KResultOr<size_t> submit_control_transfer(Transfer& transfer) override;
void get_port_status(Badge<UHCIRootHub>, u8, HubStatus&);
KResult set_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
KResult clear_port_feature(Badge<UHCIRootHub>, u8, HubFeatureSelector);
private:
explicit UHCIController(PCI::Address);
u16 read_usbcmd() { return m_io_base.offset(0).in<u16>(); }
u16 read_usbsts() { return m_io_base.offset(0x2).in<u16>(); }
u16 read_usbintr() { return m_io_base.offset(0x4).in<u16>(); }
u16 read_frnum() { return m_io_base.offset(0x6).in<u16>(); }
u32 read_flbaseadd() { return m_io_base.offset(0x8).in<u32>(); }
u8 read_sofmod() { return m_io_base.offset(0xc).in<u8>(); }
u16 read_portsc1() { return m_io_base.offset(0x10).in<u16>(); }
u16 read_portsc2() { return m_io_base.offset(0x12).in<u16>(); }
void write_usbcmd(u16 value) { m_io_base.offset(0).out(value); }
void write_usbsts(u16 value) { m_io_base.offset(0x2).out(value); }
void write_usbintr(u16 value) { m_io_base.offset(0x4).out(value); }
void write_frnum(u16 value) { m_io_base.offset(0x6).out(value); }
void write_flbaseadd(u32 value) { m_io_base.offset(0x8).out(value); }
void write_sofmod(u8 value) { m_io_base.offset(0xc).out(value); }
void write_portsc1(u16 value) { m_io_base.offset(0x10).out(value); }
void write_portsc2(u16 value) { m_io_base.offset(0x12).out(value); }
virtual bool handle_irq(const RegisterState&) override;
KResult create_structures();
void setup_schedule();
size_t poll_transfer_queue(QueueHead& transfer_queue);
TransferDescriptor* create_transfer_descriptor(Pipe& pipe, PacketID direction, size_t data_len);
KResult create_chain(Pipe& pipe, PacketID direction, Ptr32<u8>& buffer_address, size_t max_size, size_t transfer_size, TransferDescriptor** td_chain, TransferDescriptor** last_td);
void free_descriptor_chain(TransferDescriptor* first_descriptor);
QueueHead* allocate_queue_head() const;
TransferDescriptor* allocate_transfer_descriptor() const;
void reset_port(u8);
private:
IOAddress m_io_base;
OwnPtr<UHCIRootHub> m_root_hub;
Vector<QueueHead*> m_free_qh_pool;
Vector<TransferDescriptor*> m_free_td_pool;
Vector<TransferDescriptor*> m_iso_td_list;
QueueHead* m_interrupt_transfer_queue;
QueueHead* m_lowspeed_control_qh;
QueueHead* m_fullspeed_control_qh;
QueueHead* m_bulk_qh;
QueueHead* m_dummy_qh; // Needed for PIIX4 hack
OwnPtr<Memory::Region> m_framelist;
OwnPtr<Memory::Region> m_qh_pool;
OwnPtr<Memory::Region> m_td_pool;
// Bitfield containing whether a given port should signal a change in reset or not.
u8 m_port_reset_change_statuses { 0 };
// Bitfield containing whether a given port should signal a change in suspend or not.
u8 m_port_suspend_change_statuses { 0 };
};
}

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/*
* Copyright (c) 2021, Jesse Buhagiar <jooster669@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/OwnPtr.h>
#include <AK/Ptr32.h>
#include <AK/Types.h>
#include <Kernel/Bus/USB/USBTransfer.h>
namespace Kernel::USB {
enum class PacketID : u8 {
IN = 0x69,
OUT = 0xe1,
SETUP = 0x2d
};
// Transfer Descriptor register bit offsets/masks
constexpr u16 TD_CONTROL_STATUS_ACTLEN = 0x7ff;
constexpr u8 TD_CONTROL_STATUS_ACTIVE_SHIFT = 23;
constexpr u8 TD_CONTROL_STATUS_INT_ON_COMPLETE_SHIFT = 24;
constexpr u8 TD_CONTROL_STATUS_ISOCHRONOUS_SHIFT = 25;
constexpr u8 TD_CONTROL_STATUS_LS_DEVICE_SHIFT = 26;
constexpr u8 TD_CONTROL_STATUS_ERR_CTR_SHIFT_SHIFT = 27;
constexpr u8 TD_CONTROL_STATUS_SPD_SHIFT = 29;
constexpr u8 TD_TOKEN_PACKET_ID_SHIFT = 0;
constexpr u8 TD_TOKEN_DEVICE_ADDR_SHIFT = 8;
constexpr u8 TD_TOKEN_ENDPOINT_SHIFT = 15;
constexpr u8 TD_TOKEN_DATA_TOGGLE_SHIFT = 19;
constexpr u8 TD_TOKEN_MAXLEN_SHIFT = 21;
//
// Transfer Descriptor
//
// Describes a single transfer event from, or to the Universal Serial Bus.
// These are, generally, attached to Queue Heads, and then executed by the
// USB Host Controller.
// Must be 16-byte aligned
//
struct QueueHead;
struct alignas(16) TransferDescriptor final {
enum LinkPointerBits {
Terminate = 1,
QHSelect = 2,
DepthFlag = 4,
};
enum StatusBits {
Reserved = (1 << 16),
BitStuffError = (1 << 17),
CRCTimeoutError = (1 << 18),
NAKReceived = (1 << 19),
BabbleDetected = (1 << 20),
DataBufferError = (1 << 21),
Stalled = (1 << 22),
Active = (1 << 23),
ErrorMask = BitStuffError | CRCTimeoutError | NAKReceived | BabbleDetected | DataBufferError | Stalled
};
enum ControlBits {
InterruptOnComplete = (1 << 24),
IsochronousSelect = (1 << 25),
LowSpeedDevice = (1 << 26),
ShortPacketDetect = (1 << 29),
};
TransferDescriptor() = delete;
TransferDescriptor(u32 paddr)
: m_paddr(paddr)
{
}
~TransferDescriptor() = delete; // Prevent anything except placement new on this object
u32 link_ptr() const { return m_link_ptr; }
u32 paddr() const { return m_paddr; }
u32 status() const { return m_control_status; }
u32 token() const { return m_token; }
u32 buffer_ptr() const { return m_buffer_ptr; }
u16 actual_packet_length() const { return (m_control_status + 1) & 0x7ff; }
bool in_use() const { return m_in_use; }
bool stalled() const { return m_control_status & StatusBits::Stalled; }
bool last_in_chain() const { return m_link_ptr & LinkPointerBits::Terminate; }
bool active() const { return m_control_status & StatusBits::Active; }
void set_active()
{
u32 ctrl = m_control_status;
ctrl |= StatusBits::Active;
m_control_status = ctrl;
}
void set_isochronous()
{
u32 ctrl = m_control_status;
ctrl |= ControlBits::IsochronousSelect;
m_control_status = ctrl;
}
void set_interrupt_on_complete()
{
u32 ctrl = m_control_status;
ctrl |= ControlBits::InterruptOnComplete;
m_control_status = ctrl;
}
void set_lowspeed()
{
u32 ctrl = m_control_status;
ctrl |= ControlBits::LowSpeedDevice;
m_control_status = ctrl;
}
void set_error_retry_counter(u8 num_retries)
{
VERIFY(num_retries <= 3);
u32 ctrl = m_control_status;
ctrl |= (num_retries << 27);
m_control_status = ctrl;
}
void set_short_packet_detect()
{
u32 ctrl = m_control_status;
ctrl |= ControlBits::ShortPacketDetect;
m_control_status = ctrl;
}
void set_control_status(u32 control_status) { m_control_status = control_status; }
void set_in_use(bool in_use) { m_in_use = in_use; }
void set_max_len(u16 max_len)
{
VERIFY(max_len < 0x500 || max_len == 0x7ff);
m_token |= (max_len << 21);
}
void set_device_endpoint(u8 endpoint)
{
VERIFY(endpoint <= 0xf);
m_token |= (endpoint << 18);
}
void set_device_address(u8 address)
{
VERIFY(address <= 0x7f);
m_token |= (address << 8);
}
void set_data_toggle(bool toggle)
{
m_token |= ((toggle ? (1 << 19) : 0));
}
void set_packet_id(PacketID pid) { m_token |= static_cast<u32>(pid); }
void link_queue_head(u32 qh_paddr)
{
m_link_ptr = qh_paddr;
m_link_ptr |= LinkPointerBits::QHSelect;
}
void print()
{
dbgln("UHCI: TD({:#04x}) @ {:#04x}: link_ptr={:#04x}, status={:#04x}, token={:#04x}, buffer_ptr={:#04x}", this, m_paddr, m_link_ptr, (u32)m_control_status, m_token, m_buffer_ptr);
// Now let's print the flags!
dbgln("UHCI: TD({:#04x}) @ {:#04x}: link_ptr={}{}{}, status={}{}{}{}{}{}{}",
this,
m_paddr,
(last_in_chain()) ? "T " : "",
(m_link_ptr & static_cast<u32>(LinkPointerBits::QHSelect)) ? "QH " : "",
(m_link_ptr & static_cast<u32>(LinkPointerBits::DepthFlag)) ? "Vf " : "",
(m_control_status & static_cast<u32>(StatusBits::BitStuffError)) ? "BITSTUFF " : "",
(m_control_status & static_cast<u32>(StatusBits::CRCTimeoutError)) ? "CRCTIMEOUT " : "",
(m_control_status & static_cast<u32>(StatusBits::NAKReceived)) ? "NAK " : "",
(m_control_status & static_cast<u32>(StatusBits::BabbleDetected)) ? "BABBLE " : "",
(m_control_status & static_cast<u32>(StatusBits::DataBufferError)) ? "DATAERR " : "",
(stalled()) ? "STALL " : "",
(active()) ? "ACTIVE " : "");
}
// FIXME: For the love of God, use AK SMART POINTERS PLEASE!!
TransferDescriptor* next_td() { return m_next_td; }
const TransferDescriptor* next_td() const { return m_next_td; }
void set_next_td(TransferDescriptor* td) { m_next_td = td; }
TransferDescriptor* prev_td() { return m_prev_td; }
const TransferDescriptor* prev_td() const { return m_prev_td; }
void set_previous_td(TransferDescriptor* td) { m_prev_td = td; }
void insert_next_transfer_descriptor(TransferDescriptor* td)
{
m_link_ptr = td->paddr();
td->set_previous_td(this);
set_next_td(td);
// Let's set some bits for the link ptr
m_link_ptr |= static_cast<u32>(LinkPointerBits::DepthFlag);
}
void terminate() { m_link_ptr |= static_cast<u32>(LinkPointerBits::Terminate); }
void set_buffer_address(Ptr32<u8> buffer)
{
u8* buffer_address = &*buffer;
m_buffer_ptr = reinterpret_cast<uintptr_t>(buffer_address);
}
// DEBUG FUNCTIONS!
void set_token(u32 token)
{
m_token = token;
}
void set_status(u32 status)
{
m_control_status = status;
}
void free()
{
m_link_ptr = 0;
m_control_status = 0;
m_token = 0;
m_in_use = false;
}
private:
u32 m_link_ptr; // Points to another Queue Head or Transfer Descriptor
volatile u32 m_control_status; // Control and status bits
u32 m_token; // Contains all information required to fill in a USB Start Token
u32 m_buffer_ptr; // Points to a data buffer for this transaction (i.e what we want to send or recv)
// These values will be ignored by the controller, but we can use them for configuration/bookkeeping
u32 m_paddr; // Physical address where this TransferDescriptor is located
Ptr32<TransferDescriptor> m_next_td { nullptr }; // Pointer to first TD
Ptr32<TransferDescriptor> m_prev_td { nullptr }; // Pointer to first TD
bool m_in_use; // Has this TD been allocated (and therefore in use)?
};
static_assert(sizeof(TransferDescriptor) == 32); // Transfer Descriptor is always 8 Dwords
//
// Queue Head
//
// Description here please!
//
struct alignas(16) QueueHead {
enum class LinkPointerBits : u32 {
Terminate = 1,
QHSelect = 2,
};
QueueHead() = delete;
QueueHead(u32 paddr)
: m_paddr(paddr)
{
}
~QueueHead() = delete; // Prevent anything except placement new on this object
u32 link_ptr() const { return m_link_ptr; }
u32 element_link_ptr() const { return m_element_link_ptr; }
u32 paddr() const { return m_paddr; }
bool in_use() const { return m_in_use; }
void set_in_use(bool in_use) { m_in_use = in_use; }
void set_link_ptr(u32 val) { m_link_ptr = val; }
// FIXME: For the love of God, use AK SMART POINTERS PLEASE!!
QueueHead* next_qh() { return m_next_qh; }
const QueueHead* next_qh() const { return m_next_qh; }
void set_next_qh(QueueHead* qh) { m_next_qh = qh; }
QueueHead* prev_qh() { return m_prev_qh; }
const QueueHead* prev_qh() const { return m_prev_qh; }
void set_previous_qh(QueueHead* qh)
{
m_prev_qh = qh;
}
void link_next_queue_head(QueueHead* qh)
{
m_link_ptr = qh->paddr();
m_link_ptr |= static_cast<u32>(LinkPointerBits::QHSelect);
}
void attach_transfer_queue(QueueHead& qh)
{
m_element_link_ptr = qh.paddr();
m_element_link_ptr = m_element_link_ptr | static_cast<u32>(LinkPointerBits::QHSelect);
}
// FIXME: Find out best way to walk queue and free everything
void free_transfer_queue([[maybe_unused]] QueueHead* qh)
{
TODO();
}
void terminate_with_stray_descriptor(TransferDescriptor* td)
{
m_link_ptr = td->paddr();
m_link_ptr |= static_cast<u32>(LinkPointerBits::Terminate);
}
// TODO: Should we pass in an array or vector of TDs instead????
void attach_transfer_descriptor_chain(TransferDescriptor* td)
{
m_first_td = td;
m_element_link_ptr = td->paddr();
}
TransferDescriptor* get_first_td()
{
return m_first_td;
}
void terminate() { m_link_ptr |= static_cast<u32>(LinkPointerBits::Terminate); }
void terminate_element_link_ptr()
{
m_element_link_ptr = static_cast<u32>(LinkPointerBits::Terminate);
}
void set_transfer(Transfer* transfer)
{
m_transfer = transfer;
}
Transfer* transfer()
{
return m_transfer;
}
void print()
{
dbgln("UHCI: QH({:#04x}) @ {:#04x}: link_ptr={:#04x}, element_link_ptr={:#04x}", this, m_paddr, m_link_ptr, (FlatPtr)m_element_link_ptr);
}
void free()
{
m_link_ptr = 0;
m_element_link_ptr = 0;
m_first_td = nullptr;
m_transfer = nullptr;
m_in_use = false;
}
private:
u32 m_link_ptr { 0 }; // Pointer to the next horizontal object that the controller will execute after this one
volatile u32 m_element_link_ptr { 0 }; // Pointer to the first data object in the queue (can be modified by hw)
// These values will be ignored by the controller, but we can use them for configuration/bookkeeping
// Any addresses besides `paddr` are assumed virtual and can be dereferenced
u32 m_paddr { 0 }; // Physical address where this QueueHead is located
Ptr32<QueueHead> m_next_qh { nullptr }; // Next QH
Ptr32<QueueHead> m_prev_qh { nullptr }; // Previous QH
Ptr32<TransferDescriptor> m_first_td { nullptr }; // Pointer to first TD
Ptr32<Transfer> m_transfer { nullptr }; // Pointer to transfer linked to this queue head
bool m_in_use { false }; // Is this QH currently in use?
};
static_assert(sizeof(QueueHead) == 32); // Queue Head is always 8 Dwords
}

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/*
* Copyright (c) 2021, Luke Wilde <lukew@serenityos.org>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/Bus/USB/UHCI/UHCIController.h>
#include <Kernel/Bus/USB/UHCI/UHCIRootHub.h>
#include <Kernel/Bus/USB/USBClasses.h>
#include <Kernel/Bus/USB/USBConstants.h>
#include <Kernel/Bus/USB/USBEndpoint.h>
#include <Kernel/Bus/USB/USBHub.h>
#include <Kernel/Bus/USB/USBRequest.h>
namespace Kernel::USB {
static USBDeviceDescriptor uhci_root_hub_device_descriptor = {
{
sizeof(USBDeviceDescriptor), // 18 bytes long
DESCRIPTOR_TYPE_DEVICE,
},
0x0110, // USB 1.1
(u8)USB_CLASS_HUB,
0, // Hubs use subclass 0
0, // Full Speed Hub
64, // Max packet size
0x0, // Vendor ID
0x0, // Product ID
0x0110, // Product version (can be anything, currently matching usb_spec_compliance_bcd)
0, // Index of manufacturer string. FIXME: There is currently no support for string descriptors.
0, // Index of product string. FIXME: There is currently no support for string descriptors.
0, // Index of serial string. FIXME: There is currently no support for string descriptors.
1, // One configuration descriptor
};
static USBConfigurationDescriptor uhci_root_hub_configuration_descriptor = {
{
sizeof(USBConfigurationDescriptor), // 9 bytes long
DESCRIPTOR_TYPE_CONFIGURATION,
},
sizeof(USBConfigurationDescriptor) + sizeof(USBInterfaceDescriptor) + sizeof(USBEndpointDescriptor) + sizeof(USBHubDescriptor), // Combined length of configuration, interface, endpoint and hub descriptors.
1, // One interface descriptor
1, // Configuration #1
0, // Index of configuration string. FIXME: There is currently no support for string descriptors.
(1 << 7) | (1 << 6), // Bit 6 is set to indicate that the root hub is self powered. Bit 7 must always be 1.
0, // 0 mA required from the bus (self-powered)
};
static USBInterfaceDescriptor uhci_root_hub_interface_descriptor = {
{
sizeof(USBInterfaceDescriptor), // 9 bytes long
DESCRIPTOR_TYPE_INTERFACE,
},
0, // Interface #0
0, // Alternate setting
1, // One endpoint
(u8)USB_CLASS_HUB,
0, // Hubs use subclass 0
0, // Full Speed Hub
0, // Index of interface string. FIXME: There is currently no support for string descriptors
};
static USBEndpointDescriptor uhci_root_hub_endpoint_descriptor = {
{
sizeof(USBEndpointDescriptor), // 7 bytes long
DESCRIPTOR_TYPE_ENDPOINT,
},
USBEndpoint::ENDPOINT_ADDRESS_DIRECTION_IN | 1, // IN Endpoint #1
USBEndpoint::ENDPOINT_ATTRIBUTES_TRANSFER_TYPE_INTERRUPT, // Interrupt endpoint
2, // Max Packet Size FIXME: I'm not sure what this is supposed to be as it is implementation defined. 2 is the number of bytes Get Port Status returns.
0xFF, // Max possible interval
};
// NOTE: UHCI does not provide us anything for the Root Hub's Hub Descriptor.
static USBHubDescriptor uhci_root_hub_hub_descriptor = {
{
sizeof(USBHubDescriptor), // 7 bytes long. FIXME: Add the size of the VLAs at the end once they're supported.
DESCRIPTOR_TYPE_HUB,
},
UHCIController::NUMBER_OF_ROOT_PORTS, // 2 ports
0x0, // Ganged power switching, not a compound device, global over-current protection.
0x0, // UHCI ports are always powered, so there's no time from power on to power good.
0x0, // Self-powered
};
KResultOr<NonnullOwnPtr<UHCIRootHub>> UHCIRootHub::try_create(NonnullRefPtr<UHCIController> uhci_controller)
{
auto root_hub = adopt_own_if_nonnull(new (nothrow) UHCIRootHub(uhci_controller));
if (!root_hub)
return ENOMEM;
return root_hub.release_nonnull();
}
UHCIRootHub::UHCIRootHub(NonnullRefPtr<UHCIController> uhci_controller)
: m_uhci_controller(uhci_controller)
{
}
KResult UHCIRootHub::setup(Badge<UHCIController>)
{
auto hub_or_error = Hub::try_create_root_hub(m_uhci_controller, Device::DeviceSpeed::FullSpeed);
if (hub_or_error.is_error())
return hub_or_error.error();
m_hub = hub_or_error.release_value();
// NOTE: The root hub will be on the default address at this point.
// The root hub must be the first device to be created, otherwise the HCD will intercept all default address transfers as though they're targeted at the root hub.
auto result = m_hub->enumerate_device();
if (result.is_error())
return result;
// NOTE: The root hub is no longer on the default address.
result = m_hub->enumerate_and_power_on_hub();
if (result.is_error())
return result;
return KSuccess;
}
KResultOr<size_t> UHCIRootHub::handle_control_transfer(Transfer& transfer)
{
auto& request = transfer.request();
auto* request_data = transfer.buffer().as_ptr() + sizeof(USBRequestData);
if constexpr (UHCI_DEBUG) {
dbgln("UHCIRootHub: Received control transfer.");
dbgln("UHCIRootHub: Request Type: 0x{:02x}", request.request_type);
dbgln("UHCIRootHub: Request: 0x{:02x}", request.request);
dbgln("UHCIRootHub: Value: 0x{:04x}", request.value);
dbgln("UHCIRootHub: Index: 0x{:04x}", request.index);
dbgln("UHCIRootHub: Length: 0x{:04x}", request.length);
}
size_t length = 0;
switch (request.request) {
case HubRequest::GET_STATUS: {
if (request.index > UHCIController::NUMBER_OF_ROOT_PORTS)
return EINVAL;
length = min(transfer.transfer_data_size(), sizeof(HubStatus));
VERIFY(length <= sizeof(HubStatus));
HubStatus hub_status {};
if (request.index == 0) {
// If index == 0, the actual request is Get Hub Status
// UHCI does not provide "Local Power Source" or "Over-current" and their corresponding change flags.
// The members of hub_status are initialized to 0, so we can memcpy it straight away.
memcpy(request_data, (void*)&hub_status, length);
break;
}
// If index != 0, the actual request is Get Port Status
m_uhci_controller->get_port_status({}, request.index - 1, hub_status);
memcpy(request_data, (void*)&hub_status, length);
break;
}
case HubRequest::GET_DESCRIPTOR: {
u8 descriptor_type = request.value >> 8;
switch (descriptor_type) {
case DESCRIPTOR_TYPE_DEVICE:
length = min(transfer.transfer_data_size(), sizeof(USBDeviceDescriptor));
VERIFY(length <= sizeof(USBDeviceDescriptor));
memcpy(request_data, (void*)&uhci_root_hub_device_descriptor, length);
break;
case DESCRIPTOR_TYPE_CONFIGURATION:
length = min(transfer.transfer_data_size(), sizeof(USBConfigurationDescriptor));
VERIFY(length <= sizeof(USBConfigurationDescriptor));
memcpy(request_data, (void*)&uhci_root_hub_configuration_descriptor, length);
break;
case DESCRIPTOR_TYPE_INTERFACE:
length = min(transfer.transfer_data_size(), sizeof(USBInterfaceDescriptor));
VERIFY(length <= sizeof(USBInterfaceDescriptor));
memcpy(request_data, (void*)&uhci_root_hub_interface_descriptor, length);
break;
case DESCRIPTOR_TYPE_ENDPOINT:
length = min(transfer.transfer_data_size(), sizeof(USBEndpointDescriptor));
VERIFY(length <= sizeof(USBEndpointDescriptor));
memcpy(request_data, (void*)&uhci_root_hub_endpoint_descriptor, length);
break;
case DESCRIPTOR_TYPE_HUB:
length = min(transfer.transfer_data_size(), sizeof(USBHubDescriptor));
VERIFY(length <= sizeof(USBHubDescriptor));
memcpy(request_data, (void*)&uhci_root_hub_hub_descriptor, length);
break;
default:
return EINVAL;
}
break;
}
case USB_REQUEST_SET_ADDRESS:
dbgln_if(UHCI_DEBUG, "UHCIRootHub: Attempt to set address to {}, ignoring.", request.value);
if (request.value > USB_MAX_ADDRESS)
return EINVAL;
// Ignore SET_ADDRESS requests. USBDevice sets its internal address to the new allocated address that it just sent to us.
// The internal address is used to check if the request is directed at the root hub or not.
break;
case HubRequest::SET_FEATURE: {
if (request.index == 0) {
// If index == 0, the actual request is Set Hub Feature.
// UHCI does not provide "Local Power Source" or "Over-current" and their corresponding change flags.
// Therefore, ignore the request, but return an error if the value is not "Local Power Source" or "Over-current"
switch (request.value) {
case HubFeatureSelector::C_HUB_LOCAL_POWER:
case HubFeatureSelector::C_HUB_OVER_CURRENT:
break;
default:
return EINVAL;
}
break;
}
// If index != 0, the actual request is Set Port Feature.
u8 port = request.index & 0xFF;
if (port > UHCIController::NUMBER_OF_ROOT_PORTS)
return EINVAL;
auto feature_selector = (HubFeatureSelector)request.value;
auto result = m_uhci_controller->set_port_feature({}, port - 1, feature_selector);
if (result.is_error())
return result.error();
break;
}
case HubRequest::CLEAR_FEATURE: {
if (request.index == 0) {
// If index == 0, the actual request is Clear Hub Feature.
// UHCI does not provide "Local Power Source" or "Over-current" and their corresponding change flags.
// Therefore, ignore the request, but return an error if the value is not "Local Power Source" or "Over-current"
switch (request.value) {
case HubFeatureSelector::C_HUB_LOCAL_POWER:
case HubFeatureSelector::C_HUB_OVER_CURRENT:
break;
default:
return EINVAL;
}
break;
}
// If index != 0, the actual request is Clear Port Feature.
u8 port = request.index & 0xFF;
if (port > UHCIController::NUMBER_OF_ROOT_PORTS)
return EINVAL;
auto feature_selector = (HubFeatureSelector)request.value;
auto result = m_uhci_controller->clear_port_feature({}, port - 1, feature_selector);
if (result.is_error())
return result.error();
break;
}
default:
return EINVAL;
}
transfer.set_complete();
return length;
}
}

39
Kernel/Bus/USB/UHCI/UHCIRootHub.h Normal file
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/*
* Copyright (c) 2021, Luke Wilde <lukew@serenityos.org>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/NonnullOwnPtr.h>
#include <AK/NonnullRefPtr.h>
#include <Kernel/Bus/USB/USBHub.h>
#include <Kernel/Bus/USB/USBTransfer.h>
#include <Kernel/KResult.h>
namespace Kernel::USB {
class UHCIController;
class UHCIRootHub {
public:
static KResultOr<NonnullOwnPtr<UHCIRootHub>> try_create(NonnullRefPtr<UHCIController>);
UHCIRootHub(NonnullRefPtr<UHCIController>);
~UHCIRootHub() = default;
KResult setup(Badge<UHCIController>);
u8 device_address() const { return m_hub->address(); }
KResultOr<size_t> handle_control_transfer(Transfer& transfer);
void check_for_port_updates() { m_hub->check_for_port_updates(); }
private:
NonnullRefPtr<UHCIController> m_uhci_controller;
RefPtr<Hub> m_hub;
};
}