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https://github.com/RGBCube/serenity
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UserspaceEmulator: Tidy up SoftCPU's general purpose registers
This patch adds a PartAddressableRegister type, which divides a 32-bit value into separate parts needed for the EAX/AX/AL/AH register splits. Clean up the code around register access to make it a little less cumbersome to use.
This commit is contained in:
Andreas Kling
parent
b02d33bd63
commit
4d8683b632
3 changed files with 79 additions and 55 deletions
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@ -34,21 +34,13 @@ namespace UserspaceEmulator {
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SoftCPU::SoftCPU(Emulator& emulator)
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: m_emulator(emulator)
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{
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m_reg32_table[X86::RegisterEAX] = &m_eax;
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m_reg32_table[X86::RegisterEBX] = &m_ebx;
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m_reg32_table[X86::RegisterECX] = &m_ecx;
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m_reg32_table[X86::RegisterEDX] = &m_edx;
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m_reg32_table[X86::RegisterEBP] = &m_ebp;
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m_reg32_table[X86::RegisterESP] = &m_esp;
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m_reg32_table[X86::RegisterESI] = &m_esi;
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m_reg32_table[X86::RegisterEDI] = &m_edi;
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}
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void SoftCPU::dump() const
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{
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printf("eax=%08x ebx=%08x ecx=%08x edx=%08x ", m_eax, m_ebx, m_ecx, m_edx);
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printf("ebp=%08x esp=%08x esi=%08x edi=%08x ", m_ebp, m_esp, m_esi, m_edi);
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printf("o=%u s=%u z=%u a=%u p=%u c=%u\n", m_of, m_sf, m_zf, m_af, m_pf, m_cf);
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printf("eax=%08x ebx=%08x ecx=%08x edx=%08x ", eax(), ebx(), ecx(), edx());
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printf("ebp=%08x esp=%08x esi=%08x edi=%08x ", ebp(), esp(), esi(), edi());
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printf("o=%u s=%u z=%u a=%u p=%u c=%u\n", of(), sf(), zf(), af(), pf(), cf());
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}
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u32 SoftCPU::read_memory32(X86::LogicalAddress address)
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@ -68,14 +60,14 @@ void SoftCPU::write_memory32(X86::LogicalAddress address, u32 value)
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void SoftCPU::push32(u32 value)
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{
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m_esp -= sizeof(value);
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write_memory32({ get_ss(), get_esp() }, value);
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set_esp(esp() - sizeof(value));
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write_memory32({ ss(), esp() }, value);
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}
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u32 SoftCPU::pop32()
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{
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auto value = read_memory32({ get_ss(), get_esp() });
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m_esp += sizeof(value);
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auto value = read_memory32({ ss(), esp() });
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set_esp(esp() + sizeof(value));
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return value;
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}
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@ -228,7 +220,7 @@ void SoftCPU::INTO(const X86::Instruction&) { TODO(); }
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void SoftCPU::INT_imm8(const X86::Instruction& insn)
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{
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ASSERT(insn.imm8() == 0x82);
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m_eax = m_emulator.virt_syscall(m_eax, m_edx, m_ecx, m_ebx);
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set_eax(m_emulator.virt_syscall(eax(), edx(), ecx(), ebx()));
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}
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void SoftCPU::INVLPG(const X86::Instruction&) { TODO(); }
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@ -303,7 +295,7 @@ void SoftCPU::MOV_RM32_imm32(const X86::Instruction&) { TODO(); }
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void SoftCPU::MOV_RM32_reg32(const X86::Instruction& insn)
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{
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ASSERT(insn.modrm().is_register());
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*m_reg32_table[insn.modrm().register_index()] = *m_reg32_table[insn.register_index()];
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gpr32(insn.modrm().reg32()) = gpr32(insn.reg32());
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}
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void SoftCPU::MOV_RM8_imm8(const X86::Instruction&) { TODO(); }
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@ -319,7 +311,7 @@ void SoftCPU::MOV_reg32_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::MOV_reg32_imm32(const X86::Instruction& insn)
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{
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*m_reg32_table[insn.register_index()] = insn.imm32();
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gpr32(insn.reg32()) = insn.imm32();
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}
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void SoftCPU::MOV_reg8_RM8(const X86::Instruction&) { TODO(); }
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@ -377,7 +369,7 @@ void SoftCPU::POP_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::POP_reg32(const X86::Instruction& insn)
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{
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*m_reg32_table[insn.register_index()] = pop32();
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gpr32(insn.reg32()) = pop32();
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}
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void SoftCPU::PUSHA(const X86::Instruction&) { TODO(); }
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@ -400,7 +392,7 @@ void SoftCPU::PUSH_reg16(const X86::Instruction&) { TODO(); }
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void SoftCPU::PUSH_reg32(const X86::Instruction& insn)
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{
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push32(*m_reg32_table[insn.register_index()]);
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push32(gpr32(insn.reg32()));
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}
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void SoftCPU::RCL_RM16_1(const X86::Instruction&) { TODO(); }
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@ -561,8 +553,8 @@ void SoftCPU::XOR_RM32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::XOR_RM32_reg32(const X86::Instruction& insn)
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{
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ASSERT(insn.modrm().is_register());
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auto& dest = *m_reg32_table[insn.modrm().register_index()];
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auto src = *m_reg32_table[insn.register_index()];
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auto& dest = gpr32(insn.modrm().reg32());
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auto src = gpr32(insn.reg32());
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dest ^= src;
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set_cf(false);
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@ -33,6 +33,21 @@ namespace UserspaceEmulator {
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class Emulator;
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union PartAddressableRegister {
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struct {
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u32 full_u32 { 0 };
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};
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struct {
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u16 low_u16;
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u16 high_u16;
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};
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struct {
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u8 low_u8;
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u8 high_u8;
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u16 also_high_u16;
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};
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};
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class SoftCPU final : public X86::Interpreter {
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public:
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explicit SoftCPU(Emulator&);
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@ -41,13 +56,45 @@ public:
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void push32(u32);
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u32 pop32();
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u32 get_esp() const { return m_esp; }
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void set_esp(u32 value) { m_esp = value; }
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u32 gpr32(X86::RegisterIndex32 reg) const { return m_gpr[reg].full_u32; }
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u32& gpr32(X86::RegisterIndex32 reg) { return m_gpr[reg].full_u32; }
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u16 get_cs() const { return 0x18; }
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u16 get_ds() const { return 0x20; }
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u16 get_es() const { return 0x20; }
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u16 get_ss() const { return 0x20; }
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u32 eax() const { return gpr32(X86::RegisterEAX); }
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u32 ebx() const { return gpr32(X86::RegisterEBX); }
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u32 ecx() const { return gpr32(X86::RegisterECX); }
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u32 edx() const { return gpr32(X86::RegisterEDX); }
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u32 esp() const { return gpr32(X86::RegisterESP); }
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u32 ebp() const { return gpr32(X86::RegisterEBP); }
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u32 esi() const { return gpr32(X86::RegisterESI); }
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u32 edi() const { return gpr32(X86::RegisterEDI); }
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void set_eax(u32 value) { gpr32(X86::RegisterEAX) = value; }
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void set_ebx(u32 value) { gpr32(X86::RegisterEBX) = value; }
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void set_ecx(u32 value) { gpr32(X86::RegisterECX) = value; }
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void set_edx(u32 value) { gpr32(X86::RegisterEDX) = value; }
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void set_ebp(u32 value) { gpr32(X86::RegisterEBP) = value; }
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void set_esp(u32 value) { gpr32(X86::RegisterESP) = value; }
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void set_esi(u32 value) { gpr32(X86::RegisterESI) = value; }
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void set_edi(u32 value) { gpr32(X86::RegisterEDI) = value; }
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bool of() const { return m_of; }
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bool sf() const { return m_sf; }
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bool zf() const { return m_zf; }
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bool af() const { return m_af; }
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bool pf() const { return m_pf; }
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bool cf() const { return m_cf; }
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void set_of(bool value) { m_of = value; }
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void set_sf(bool value) { m_sf = value; }
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void set_zf(bool value) { m_zf = value; }
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void set_af(bool value) { m_af = value; }
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void set_pf(bool value) { m_pf = value; }
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void set_cf(bool value) { m_cf = value; }
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u16 cs() const { return 0x18; }
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u16 ds() const { return 0x20; }
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u16 es() const { return 0x20; }
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u16 ss() const { return 0x20; }
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u32 read_memory32(X86::LogicalAddress);
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void write_memory32(X86::LogicalAddress, u32);
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@ -526,30 +573,7 @@ private:
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private:
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Emulator& m_emulator;
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bool get_of() const { return m_of; }
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bool get_sf() const { return m_sf; }
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bool get_zf() const { return m_zf; }
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bool get_af() const { return m_af; }
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bool get_pf() const { return m_pf; }
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bool get_cf() const { return m_cf; }
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void set_of(bool value) { m_of = value; }
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void set_sf(bool value) { m_sf = value; }
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void set_zf(bool value) { m_zf = value; }
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void set_af(bool value) { m_af = value; }
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void set_pf(bool value) { m_pf = value; }
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void set_cf(bool value) { m_cf = value; }
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u32* m_reg32_table[8];
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u32 m_eax { 0 };
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u32 m_ebx { 0 };
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u32 m_ecx { 0 };
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u32 m_edx { 0 };
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u32 m_esp { 0 };
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u32 m_ebp { 0 };
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u32 m_esi { 0 };
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u32 m_edi { 0 };
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PartAddressableRegister m_gpr[8];
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bool m_of { false };
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bool m_sf { false };
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@ -124,7 +124,7 @@ enum MMXRegisterIndex {
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class LogicalAddress {
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public:
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LogicalAddress() {}
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LogicalAddress() { }
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LogicalAddress(u16 selector, u32 offset)
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: m_selector(selector)
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, m_offset(offset)
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@ -200,6 +200,10 @@ public:
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bool is_register() const { return m_register_index != 0xffffffff; }
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unsigned register_index() const { return m_register_index; }
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RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
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RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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SegmentRegister segment() const
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{
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ASSERT(!is_register());
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@ -208,7 +212,7 @@ public:
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u32 offset();
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private:
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MemoryOrRegisterReference() {}
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MemoryOrRegisterReference() { }
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String to_string() const;
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String to_string_a16() const;
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@ -245,7 +249,7 @@ typedef void (Interpreter::*InstructionHandler)(const Instruction&);
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class Instruction {
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public:
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static Instruction from_stream(InstructionStream&, bool o32, bool a32);
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~Instruction() {}
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~Instruction() { }
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MemoryOrRegisterReference& modrm() const
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{
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@ -321,6 +325,10 @@ public:
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bool has_sub_op() const { return m_has_sub_op; }
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unsigned register_index() const { return m_register_index; }
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RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
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RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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SegmentRegister segment_register() const { return static_cast<SegmentRegister>(register_index()); }
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u8 cc() const { return m_has_sub_op ? m_sub_op & 0xf : m_op & 0xf; }
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