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Kernel: Move the Storage directory to be a new directory under Devices
The Storage subsystem, like the Audio and HID subsystems, exposes Unix device files (for example, in the /dev directory). To ensure consistency across the repository, we should make the Storage subsystem to reside in the Kernel/Devices directory like the two other mentioned subsystems.
This commit is contained in:
Liav A
Jelle Raaijmakers
parent
f3a58f3a5a
commit
500b7b08d6
59 changed files with 133 additions and 133 deletions
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/*
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* Copyright (c) 2021-2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Atomic.h>
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#include <AK/BuiltinWrappers.h>
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#include <AK/OwnPtr.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/CommandLine.h>
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#include <Kernel/Library/LockRefPtr.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Storage/ATA/AHCI/Controller.h>
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#include <Kernel/Storage/ATA/AHCI/InterruptHandler.h>
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namespace Kernel {
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UNMAP_AFTER_INIT ErrorOr<NonnullRefPtr<AHCIController>> AHCIController::initialize(PCI::DeviceIdentifier const& pci_device_identifier)
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{
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auto controller = adopt_ref_if_nonnull(new (nothrow) AHCIController(pci_device_identifier)).release_nonnull();
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TRY(controller->initialize_hba(pci_device_identifier));
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return controller;
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}
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ErrorOr<void> AHCIController::reset()
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{
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dmesgln_pci(*this, "{}: AHCI controller reset", device_identifier().address());
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{
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SpinlockLocker locker(m_hba_control_lock);
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hba().control_regs.ghc = 1;
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dbgln_if(AHCI_DEBUG, "{}: AHCI Controller reset", device_identifier().address());
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full_memory_barrier();
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size_t retry = 0;
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// Note: The HBA is locked or hung if we waited more than 1 second!
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while (true) {
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if (retry > 1000)
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return Error::from_errno(ETIMEDOUT);
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if (!(hba().control_regs.ghc & 1))
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break;
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microseconds_delay(1000);
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retry++;
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}
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// Note: Turn on AHCI HBA and Global HBA Interrupts.
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full_memory_barrier();
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hba().control_regs.ghc = (1 << 31) | (1 << 1);
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full_memory_barrier();
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}
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// Note: According to the AHCI spec the PI register indicates which ports are exposed by the HBA.
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// It is loaded by the BIOS. It indicates which ports that the HBA supports are available for software to use.
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// For example, on an HBA that supports 6 ports as indicated in CAP.NP, only ports 1 and 3 could be available,
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// with ports 0, 2, 4, and 5 being unavailable.
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// Which means that even without clearing the AHCI ports array, we are never able to encounter
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// a case that we would have stale left-over ports in there. We still clear the array
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// for the sake of clarity and completeness, as it doesn't harm anything anyway.
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m_ports.fill({});
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auto implemented_ports = AHCI::MaskedBitField((u32 volatile&)(hba().control_regs.pi));
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for (auto index : implemented_ports.to_vector()) {
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auto port = AHCIPort::create(*this, m_hba_capabilities, static_cast<volatile AHCI::PortRegisters&>(hba().port_regs[index]), index).release_value_but_fixme_should_propagate_errors();
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m_ports[index] = port;
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port->reset();
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}
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return {};
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}
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ErrorOr<void> AHCIController::shutdown()
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{
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return Error::from_errno(ENOTIMPL);
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}
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size_t AHCIController::devices_count() const
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{
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SpinlockLocker locker(m_hba_control_lock);
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size_t count = 0;
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for (auto port : m_ports) {
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if (port && port->connected_device())
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count++;
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}
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return count;
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}
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void AHCIController::start_request(ATADevice const& device, AsyncBlockDeviceRequest& request)
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{
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auto port = m_ports[device.ata_address().port];
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VERIFY(port);
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port->start_request(request);
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}
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void AHCIController::complete_current_request(AsyncDeviceRequest::RequestResult)
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{
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VERIFY_NOT_REACHED();
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}
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volatile AHCI::PortRegisters& AHCIController::port(size_t port_number) const
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{
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VERIFY(port_number < (size_t)AHCI::Limits::MaxPorts);
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return static_cast<volatile AHCI::PortRegisters&>(hba().port_regs[port_number]);
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}
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volatile AHCI::HBA& AHCIController::hba() const
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{
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return const_cast<AHCI::HBA&>(*m_hba_mapping);
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}
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UNMAP_AFTER_INIT AHCIController::AHCIController(PCI::DeviceIdentifier const& pci_device_identifier)
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: ATAController()
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, PCI::Device(const_cast<PCI::DeviceIdentifier&>(pci_device_identifier))
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{
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}
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UNMAP_AFTER_INIT AHCI::HBADefinedCapabilities AHCIController::capabilities() const
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{
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u32 capabilities = hba().control_regs.cap;
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u32 extended_capabilities = hba().control_regs.cap2;
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dbgln_if(AHCI_DEBUG, "{}: AHCI Controller Capabilities = {:#08x}, Extended Capabilities = {:#08x}", device_identifier().address(), capabilities, extended_capabilities);
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return (AHCI::HBADefinedCapabilities) {
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(capabilities & 0b11111) + 1,
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((capabilities >> 8) & 0b11111) + 1,
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(u8)((capabilities >> 20) & 0b1111),
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(capabilities & (u32)(AHCI::HBACapabilities::SXS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::EMS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::CCCS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::PSC)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SSC)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::PMD)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::FBSS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SPM)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SAM)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SCLO)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SAL)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SALP)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SSS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SMPS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SSNTF)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SNCQ)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::S64A)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::BOH)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::NVMP)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::APST)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::SDS)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::SADM)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::DESO)) != 0
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};
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}
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UNMAP_AFTER_INIT ErrorOr<Memory::TypedMapping<AHCI::HBA volatile>> AHCIController::map_default_hba_region(PCI::DeviceIdentifier const& pci_device_identifier)
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{
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return Memory::map_typed_writable<AHCI::HBA volatile>(PhysicalAddress(PCI::get_BAR5(pci_device_identifier)));
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}
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AHCIController::~AHCIController() = default;
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UNMAP_AFTER_INIT ErrorOr<void> AHCIController::initialize_hba(PCI::DeviceIdentifier const& pci_device_identifier)
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{
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m_hba_mapping = TRY(map_default_hba_region(pci_device_identifier));
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m_hba_capabilities = capabilities();
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u32 version = hba().control_regs.version;
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hba().control_regs.ghc = 0x80000000; // Ensure that HBA knows we are AHCI aware.
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PCI::enable_bus_mastering(device_identifier());
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TRY(reserve_irqs(1, true));
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auto irq = MUST(allocate_irq(0));
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enable_global_interrupts();
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auto implemented_ports = AHCI::MaskedBitField((u32 volatile&)(hba().control_regs.pi));
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m_irq_handler = AHCIInterruptHandler::create(*this, irq, implemented_ports).release_value_but_fixme_should_propagate_errors();
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TRY(reset());
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dbgln_if(AHCI_DEBUG, "{}: AHCI Controller Version = {:#08x}", device_identifier().address(), version);
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dbgln("{}: AHCI command list entries count - {}", device_identifier().address(), m_hba_capabilities.max_command_list_entries_count);
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return {};
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}
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void AHCIController::handle_interrupt_for_port(Badge<AHCIInterruptHandler>, u32 port_index) const
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{
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auto port = m_ports[port_index];
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VERIFY(port);
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port->handle_interrupt();
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}
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void AHCIController::disable_global_interrupts() const
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{
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hba().control_regs.ghc = hba().control_regs.ghc & 0xfffffffd;
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}
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void AHCIController::enable_global_interrupts() const
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{
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hba().control_regs.ghc = hba().control_regs.ghc | (1 << 1);
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}
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LockRefPtr<StorageDevice> AHCIController::device_by_port(u32 port_index) const
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{
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SpinlockLocker locker(m_hba_control_lock);
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auto port = m_ports[port_index];
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if (!port)
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return {};
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SpinlockLocker port_hard_locker(port->m_hard_lock);
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return port->connected_device();
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}
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LockRefPtr<StorageDevice> AHCIController::device(u32 index) const
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{
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Vector<NonnullLockRefPtr<StorageDevice>> connected_devices;
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u32 pi = hba().control_regs.pi;
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u32 bit = bit_scan_forward(pi);
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while (bit) {
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dbgln_if(AHCI_DEBUG, "Checking implemented port {}, pi {:b}", bit - 1, pi);
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pi &= ~(1u << (bit - 1));
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auto checked_device = device_by_port(bit - 1);
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bit = bit_scan_forward(pi);
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if (checked_device.is_null())
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continue;
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connected_devices.append(checked_device.release_nonnull());
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}
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dbgln_if(AHCI_DEBUG, "Connected device count: {}, Index: {}", connected_devices.size(), index);
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if (index >= connected_devices.size())
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return nullptr;
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return connected_devices[index];
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}
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}
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