From 5791072280aa4093159ae54f74ce80434650429b Mon Sep 17 00:00:00 2001 From: konrad Date: Sun, 8 Jan 2023 12:22:47 +0100 Subject: [PATCH] Kernel: Detect Aarch64 virtual address bit width with CPU ID registers --- Kernel/Arch/aarch64/CPUID.cpp | 16 ++++++++++++++++ Kernel/Arch/aarch64/CPUID.h | 1 + Kernel/Arch/aarch64/Processor.cpp | 2 ++ Kernel/Arch/aarch64/Processor.h | 4 ++-- 4 files changed, 21 insertions(+), 2 deletions(-) diff --git a/Kernel/Arch/aarch64/CPUID.cpp b/Kernel/Arch/aarch64/CPUID.cpp index d0376e876a..85dea8d834 100644 --- a/Kernel/Arch/aarch64/CPUID.cpp +++ b/Kernel/Arch/aarch64/CPUID.cpp @@ -1504,4 +1504,20 @@ u8 detect_physical_address_bit_width() } } +u8 detect_virtual_address_bit_width() +{ + auto memory_model_feature_register_2 = Aarch64::ID_AA64MMFR2_EL1::read(); + + switch (memory_model_feature_register_2.VARange) { + case 0b0000: + return 48; // 256TB + case 0b0001: + return 52; // 4PB (only for 64KB translation granule) + case 0b0010: + return 56; // 64PB (applies for FEAT_D128) + default: + VERIFY_NOT_REACHED(); + } +} + } diff --git a/Kernel/Arch/aarch64/CPUID.h b/Kernel/Arch/aarch64/CPUID.h index 4c914c78bc..e4b8fc36d2 100644 --- a/Kernel/Arch/aarch64/CPUID.h +++ b/Kernel/Arch/aarch64/CPUID.h @@ -278,5 +278,6 @@ StringView cpu_feature_to_description(CPUFeature::Type const&); NonnullOwnPtr build_cpu_feature_names(CPUFeature::Type const&); u8 detect_physical_address_bit_width(); +u8 detect_virtual_address_bit_width(); } diff --git a/Kernel/Arch/aarch64/Processor.cpp b/Kernel/Arch/aarch64/Processor.cpp index 471e77b2db..3593de1bac 100644 --- a/Kernel/Arch/aarch64/Processor.cpp +++ b/Kernel/Arch/aarch64/Processor.cpp @@ -34,6 +34,7 @@ void Processor::install(u32 cpu) m_cpu = cpu; m_features = detect_cpu_features(); m_physical_address_bit_width = detect_physical_address_bit_width(); + m_virtual_address_bit_width = detect_virtual_address_bit_width(); initialize_exceptions(cpu); @@ -44,6 +45,7 @@ void Processor::initialize() { dmesgln("CPU[{}]: Supports {}", m_cpu, build_cpu_feature_names(m_features)); dmesgln("CPU[{}]: Physical address bit width: {}", m_cpu, m_physical_address_bit_width); + dmesgln("CPU[{}]: Virtual address bit width: {}", m_cpu, m_virtual_address_bit_width); } [[noreturn]] void Processor::halt() diff --git a/Kernel/Arch/aarch64/Processor.h b/Kernel/Arch/aarch64/Processor.h index 2111369f02..a21739702e 100644 --- a/Kernel/Arch/aarch64/Processor.h +++ b/Kernel/Arch/aarch64/Processor.h @@ -89,8 +89,7 @@ public: ALWAYS_INLINE u8 virtual_address_bit_width() const { - TODO_AARCH64(); - return 0; + return m_virtual_address_bit_width; } ALWAYS_INLINE static bool is_initialized() @@ -286,6 +285,7 @@ private: u32 m_cpu; CPUFeature::Type m_features; u8 m_physical_address_bit_width; + u8 m_virtual_address_bit_width; Thread* m_current_thread; Thread* m_idle_thread;