Kernel: Expand PATA driver to support multiple hard drives (#365)

The previous implementation of the PIIX3/4 PATA/IDE channel driver only
supported a single drive, as the object model was wrong (the channel
inherits the IRQ, not the disk drive itself). This fixes it by 'attaching'
two `PATADiskDevices` to a `PATAChannel`, which makes more sense.

The reading/writing code is presented as is, which violates the spec
outlined by Seagate in the linked datasheet. That spec is rather old,
so it might not be 100% up to date, though may cause issues on real
hardware, so until we can actually test it, this will suffice.

Kernel/Devices/PATAChannel.h

@@ -0,0 +1,72 @@
+//
+// Parallel ATA (PATA) controller driver
+//
+// This driver describes a logical PATA Channel. Each channel can connect up to 2
+// IDE Hard Disk Drives. The drives themselves can be either the master drive (hd0)
+// or the slave drive (hd1).
+//
+// More information about the ATA spec for PATA can be found here:
+//      ftp://ftp.seagate.com/acrobat/reference/111-1c.pdf
+//
+#pragma once
+
+#include <AK/OwnPtr.h>
+#include <AK/RefPtr.h>
+#include <Kernel/IRQHandler.h>
+#include <Kernel/Lock.h>
+#include <Kernel/PCI.h>
+#include <Kernel/VM/PhysicalAddress.h>
+#include <Kernel/VM/PhysicalPage.h>
+
+struct PhysicalRegionDescriptor {
+    PhysicalAddress offset;
+    u16 size { 0 };
+    u16 end_of_table { 0 };
+};
+
+class PATADiskDevice;
+class PATAChannel final : public IRQHandler {
+    friend class PATADiskDevice;
+    AK_MAKE_ETERNAL
+public:
+    enum class ChannelType : u8 {
+        Primary,
+        Secondary
+    };
+
+public:
+    static OwnPtr<PATAChannel> create(ChannelType type);
+    explicit PATAChannel(ChannelType);
+    virtual ~PATAChannel() override;
+
+    RefPtr<PATADiskDevice> master_device() { return m_master; };
+    RefPtr<PATADiskDevice> slave_device() { return m_slave; };
+
+private:
+    //^ IRQHandler
+    virtual void handle_irq() override;
+
+    void initialize();
+    void detect_disks();
+
+    bool wait_for_irq();
+    bool ata_read_sectors_with_dma(u32, u16, u8*, bool);
+    bool ata_write_sectors_with_dma(u32, u16, const u8*, bool);
+    bool ata_read_sectors(u32, u16, u8*, bool);
+    bool ata_write_sectors(u32, u16, const u8*, bool);
+
+    // Data members
+    u8 m_channel_number { 0 }; // Channel number. 0 = master, 1 = slave
+    u16 m_io_base { 0x1F0 };
+    volatile u8 m_device_error { 0 };
+    volatile bool m_interrupted { false };
+
+    PCI::Address m_pci_address;
+    PhysicalRegionDescriptor m_prdt;
+    RefPtr<PhysicalPage> m_dma_buffer_page;
+    u16 m_bus_master_base { 0 };
+    Lockable<bool> m_dma_enabled;
+
+    RefPtr<PATADiskDevice> m_master;
+    RefPtr<PATADiskDevice> m_slave;
+};