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https://github.com/RGBCube/serenity
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Kernel: Replace inline asm with typesafe static member functions
This commit is contained in:
James Mintram
Brian Gianforcaro
parent
4bc5936a57
commit
5a75bd31b0
4 changed files with 473 additions and 226 deletions
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@ -1,215 +0,0 @@
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/*
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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namespace Kernel {
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struct Aarch64_SCTLR_EL1 {
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int M : 1;
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int A : 1;
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int C : 1;
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int SA : 1;
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int SA0 : 1;
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int CP15BEN : 1;
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int _reserved6 : 1 = 0;
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int ITD : 1;
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int SED : 1;
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int UMA : 1;
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int _reserved10 : 1 = 0;
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int _reserved11 : 1 = 1;
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int I : 1;
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int EnDB : 1;
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int DZE : 1;
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int UCT : 1;
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int nTWI : 1;
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int _reserved17 : 1 = 0;
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int nTWE : 1;
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int WXN : 1;
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int _reserved20 : 1 = 1;
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int IESB : 1;
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int _reserved22 : 1 = 1;
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int SPAN : 1;
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int E0E : 1;
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int EE : 1;
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int UCI : 1;
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int EnDA : 1;
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int nTLSMD : 1;
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int LSMAOE : 1;
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int EnIB : 1;
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int EnIA : 1;
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int _reserved32 : 3 = 0;
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int BT0 : 1;
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int BT1 : 1;
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int ITFSB : 1;
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int TCF0 : 2;
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int TCF : 2;
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int ATA0 : 1;
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int ATA : 1;
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int DSSBS : 1;
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int TWEDEn : 1;
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int TWEDEL : 4;
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int _reserved50 : 4 = 0;
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int EnASR : 1;
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int EnAS0 : 1;
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int EnALS : 1;
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int EPAN : 1;
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int _reserved58 : 6 = 0;
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};
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static_assert(sizeof(Aarch64_SCTLR_EL1) == 8);
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struct Aarch64_HCR_EL2 {
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int VM : 1;
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int SWIO : 1;
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int PTW : 1;
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int FMO : 1;
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int IMO : 1;
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int AMO : 1;
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int VF : 1;
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int VI : 1;
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int VSE : 1;
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int FB : 1;
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int BSU : 2;
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int DC : 1;
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int TWI : 1;
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int TWE : 1;
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int TID0 : 1;
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int TID1 : 1;
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int TID2 : 1;
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int TID3 : 1;
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int TSC : 1;
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int TIPDCP : 1;
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int TACR : 1;
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int TSW : 1;
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int TPCF : 1;
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int TPU : 1;
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int TTLB : 1;
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int TVM : 1;
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int TGE : 1;
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int TDZ : 1;
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int HCD : 1;
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int TRVM : 1;
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int RW : 1;
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int CD : 1;
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int ID : 1;
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int E2H : 1;
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int TLOR : 1;
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int TERR : 1;
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int MIOCNCE : 1;
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int _reserved39 : 1 = 0;
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int APK : 1 = 0;
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int API : 1 = 0;
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int NV : 1 = 0;
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int NV1 : 1 = 0;
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int AT : 1 = 0;
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int _reserved45 : 18 = 0;
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};
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static_assert(sizeof(Aarch64_HCR_EL2) == 8);
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struct Aarch64_SCR_EL3 {
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int NS : 1;
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int IRQ : 1;
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int FIQ : 1;
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int EA : 1;
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int _reserved4 : 1 = 1;
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int _reserved5 : 1 = 1;
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int _reserved6 : 1 = 0;
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int SMD : 1;
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int HCE : 1;
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int SIF : 1;
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int RW : 1;
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int ST : 1;
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int TWI : 1;
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int TWE : 1;
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int TLOR : 1;
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int TERR : 1;
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int APK : 1;
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int API : 1;
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int EEL2 : 1;
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int EASE : 1;
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int NMEA : 1;
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int FIEN : 1;
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int _reserved22 : 3 = 0;
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int EnSCXT : 1;
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int ATA : 1;
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int FGTEn : 1;
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int ECVEn : 1;
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int TWEDEn : 1;
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int TWEDEL : 4;
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int _reserved34 : 1 = 0;
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int AMVOFFEN : 1;
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int EnAS0 : 1;
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int ADEn : 1;
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int HXEn : 1;
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int _reserved39 : 14 = 0;
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};
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static_assert(sizeof(Aarch64_SCR_EL3) == 8);
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struct Aarch64_SPSR_EL2 {
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enum Mode : uint16_t {
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EL0t = 0b0000,
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EL1t = 0b0100,
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EL1h = 0b0101,
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EL2t = 0b1000,
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EL2h = 0b1001
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};
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Mode M : 4;
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int M_4 : 1 = 0;
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int _reserved5 : 1 = 0;
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int F : 1;
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int I : 1;
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int A : 1;
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int D : 1;
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int BTYPE : 2;
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int SSBS : 1;
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int _reserved13 : 7 = 0;
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int IL : 1;
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int SS : 1;
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int PAN : 1;
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int UA0 : 1;
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int DIT : 1;
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int TCO : 1;
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int _reserved26 : 2 = 0;
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int V : 1;
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int C : 1;
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int Z : 1;
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int N : 1;
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int _reserved32 : 32 = 0;
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};
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static_assert(sizeof(Aarch64_SPSR_EL2) == 8);
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struct Aarch64_SPSR_EL3 {
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enum Mode : uint16_t {
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EL0t = 0b0000,
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EL1t = 0b0100,
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EL1h = 0b0101,
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EL2t = 0b1000,
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EL2h = 0b1001,
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EL3t = 0b1100,
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EL3h = 0b1101
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};
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Mode M : 4;
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int M_4 : 1 = 0;
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int _reserved5 : 1 = 0;
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int F : 1;
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int I : 1;
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int A : 1;
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int D : 1;
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int _reserved10 : 10 = 0;
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int IL : 1;
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int SS : 1;
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int PAN : 1;
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int UA0 : 1;
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int _reserved24 : 4 = 0;
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int V : 1;
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int C : 1;
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int Z : 1;
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int N : 1;
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int _reserved32 : 32 = 0;
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};
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static_assert(sizeof(Aarch64_SPSR_EL3) == 8);
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}
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@ -6,6 +6,7 @@
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*/
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#include <AK/Types.h>
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#include <Kernel/Arch/aarch64/Aarch64Registers.h>
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#include <Kernel/Prekernel/Arch/aarch64/Aarch64_asm_utils.h>
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#include <Kernel/Prekernel/Arch/aarch64/BootPPMParser.h>
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#include <Kernel/Prekernel/Arch/aarch64/Framebuffer.h>
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@ -140,8 +141,7 @@ static void set_up_el1_mode()
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// Enable memory access alignment check
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system_control_register_el1.A = 1;
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// Set the register
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asm("msr sctlr_el1, %[value]" ::[value] "r"(system_control_register_el1));
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Kernel::Aarch64_SCTLR_EL1::write(system_control_register_el1);
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}
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static void set_up_el2_mode()
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@ -151,8 +151,7 @@ static void set_up_el2_mode()
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// EL1 to use 64-bit mode
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hypervisor_configuration_register_el2.RW = 1;
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// Set the register
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asm("msr hcr_el2, %[value]" ::[value] "r"(hypervisor_configuration_register_el2));
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Kernel::Aarch64_HCR_EL2::write(hypervisor_configuration_register_el2);
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}
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static void set_up_el3_mode()
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@ -168,8 +167,7 @@ static void set_up_el3_mode()
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// Enable Hypervisor instructions at all levels
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secure_configuration_register_el3.HCE = 1;
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// Set the register
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asm("msr scr_el3, %[value]" ::[value] "r"(secure_configuration_register_el3));
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Kernel::Aarch64_SCR_EL3::write(secure_configuration_register_el3);
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}
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[[noreturn]] static void jump_to_os_start_from_el2()
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@ -185,8 +183,7 @@ static void set_up_el3_mode()
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// Indicate EL1 as exception origin mode (so we go back there)
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saved_program_status_register_el2.M = Kernel::Aarch64_SPSR_EL2::Mode::EL1h;
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// Set the register
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asm("msr spsr_el2, %[value]" ::[value] "r"(saved_program_status_register_el2));
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Kernel::Aarch64_SPSR_EL2::write(saved_program_status_register_el2);
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// This will jump into os_start()
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return_from_el2();
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@ -205,8 +202,7 @@ static void set_up_el3_mode()
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// Indicate EL1 as exception origin mode (so we go back there)
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saved_program_status_register_el3.M = Kernel::Aarch64_SPSR_EL3::Mode::EL1h;
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// Set the register
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asm("msr spsr_el3, %[value]" ::[value] "r"(saved_program_status_register_el3));
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Kernel::Aarch64_SPSR_EL3::write(saved_program_status_register_el3);
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// This will jump into os_start() below
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return_from_el3();
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