mirror of
https://github.com/RGBCube/serenity
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LibJIT+LibJS: Move JIT::Assembler into a new LibJIT library
This will allow other parts of the system to generate machine code at runtime. :^)
This commit is contained in:
Andreas Kling
parent
bfb527e614
commit
5b87d26027
7 changed files with 15 additions and 6 deletions
504
Userland/Libraries/LibJIT/Assembler.h
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504
Userland/Libraries/LibJIT/Assembler.h
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@ -0,0 +1,504 @@
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/*
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* Copyright (c) 2023, Andreas Kling <kling@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Vector.h>
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namespace JIT {
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struct Assembler {
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Assembler(Vector<u8>& output)
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: m_output(output)
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{
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}
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Vector<u8>& m_output;
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enum class Reg {
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RAX = 0,
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RCX = 1,
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RDX = 2,
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RBX = 3,
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RSP = 4,
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RBP = 5,
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RSI = 6,
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RDI = 7,
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R8 = 8,
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R9 = 9,
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R10 = 10,
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R11 = 11,
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R12 = 12,
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R13 = 13,
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R14 = 14,
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R15 = 15,
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};
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struct Operand {
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enum class Type {
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Reg,
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Imm8,
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Imm32,
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Imm64,
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Mem64BaseAndOffset,
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};
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Type type {};
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Reg reg {};
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u64 offset_or_immediate { 0 };
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static Operand Register(Reg reg)
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{
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Operand operand;
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operand.type = Type::Reg;
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operand.reg = reg;
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return operand;
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}
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static Operand Imm8(u8 imm8)
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{
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Operand operand;
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operand.type = Type::Imm8;
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operand.offset_or_immediate = imm8;
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return operand;
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}
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static Operand Imm32(u32 imm32)
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{
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Operand operand;
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operand.type = Type::Imm32;
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operand.offset_or_immediate = imm32;
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return operand;
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}
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static Operand Imm64(u64 imm64)
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{
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Operand operand;
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operand.type = Type::Imm64;
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operand.offset_or_immediate = imm64;
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return operand;
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}
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static Operand Mem64BaseAndOffset(Reg base, u64 offset)
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{
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Operand operand;
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operand.type = Type::Mem64BaseAndOffset;
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operand.reg = base;
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operand.offset_or_immediate = offset;
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return operand;
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}
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};
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static constexpr u8 encode_reg(Reg reg)
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{
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return to_underlying(reg) & 0x7;
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}
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void shift_right(Operand dst, Operand count)
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{
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VERIFY(dst.type == Operand::Type::Reg);
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VERIFY(count.type == Operand::Type::Imm8);
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0xc1);
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emit8(0xe8 | encode_reg(dst.reg));
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emit8(count.offset_or_immediate);
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}
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void mov(Operand dst, Operand src)
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{
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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if (src.reg == dst.reg)
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return;
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x89);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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return;
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}
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm64) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0xb8 | encode_reg(dst.reg));
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emit64(src.offset_or_immediate);
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return;
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}
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if (dst.type == Operand::Type::Mem64BaseAndOffset && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x89);
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emit8(0x80 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit32(dst.offset_or_immediate);
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return;
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}
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Mem64BaseAndOffset) {
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emit8(0x48
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| ((to_underlying(dst.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(src.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x8b);
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emit8(0x80 | (encode_reg(dst.reg) << 3) | encode_reg(src.reg));
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emit32(src.offset_or_immediate);
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return;
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}
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VERIFY_NOT_REACHED();
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}
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void emit8(u8 value)
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{
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m_output.append(value);
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}
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void emit32(u32 value)
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{
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m_output.append((value >> 0) & 0xff);
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m_output.append((value >> 8) & 0xff);
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m_output.append((value >> 16) & 0xff);
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m_output.append((value >> 24) & 0xff);
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}
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void emit64(u64 value)
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{
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m_output.append((value >> 0) & 0xff);
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m_output.append((value >> 8) & 0xff);
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m_output.append((value >> 16) & 0xff);
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m_output.append((value >> 24) & 0xff);
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m_output.append((value >> 32) & 0xff);
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m_output.append((value >> 40) & 0xff);
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m_output.append((value >> 48) & 0xff);
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m_output.append((value >> 56) & 0xff);
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}
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struct Label {
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size_t offset_of_label_in_instruction_stream { 0 };
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Vector<size_t> jump_slot_offsets_in_instruction_stream;
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void add_jump(size_t offset)
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{
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jump_slot_offsets_in_instruction_stream.append(offset);
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}
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void link(Assembler& assembler)
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{
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link_to(assembler, assembler.m_output.size());
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}
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void link_to(Assembler& assembler, size_t link_offset)
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{
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offset_of_label_in_instruction_stream = link_offset;
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for (auto offset_in_instruction_stream : jump_slot_offsets_in_instruction_stream) {
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auto offset = offset_of_label_in_instruction_stream - offset_in_instruction_stream;
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auto jump_slot = offset_in_instruction_stream - 4;
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assembler.m_output[jump_slot + 0] = (offset >> 0) & 0xff;
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assembler.m_output[jump_slot + 1] = (offset >> 8) & 0xff;
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assembler.m_output[jump_slot + 2] = (offset >> 16) & 0xff;
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assembler.m_output[jump_slot + 3] = (offset >> 24) & 0xff;
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}
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}
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};
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[[nodiscard]] Label make_label()
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{
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return { .offset_of_label_in_instruction_stream = m_output.size() };
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}
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[[nodiscard]] Label jump()
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{
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// jmp target (RIP-relative 32-bit offset)
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emit8(0xe9);
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emit32(0xdeadbeef);
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auto label = make_label();
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label.add_jump(m_output.size());
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return label;
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}
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void jump(Label& label)
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{
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// jmp target (RIP-relative 32-bit offset)
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emit8(0xe9);
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emit32(0xdeadbeef);
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label.add_jump(m_output.size());
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}
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void jump(Operand op)
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{
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if (op.type == Operand::Type::Reg) {
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if (to_underlying(op.reg) >= 8)
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emit8(0x41);
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emit8(0xff);
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emit8(0xe0 | encode_reg(op.reg));
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void verify_not_reached()
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{
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// ud2
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emit8(0x0f);
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emit8(0x0b);
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}
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void cmp(Operand lhs, Operand rhs)
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{
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if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(rhs.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x39);
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emit8(0xc0 | (encode_reg(rhs.reg) << 3) | encode_reg(lhs.reg));
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} else if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Imm32) {
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emit8(0x48 | ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xf8 | encode_reg(lhs.reg));
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emit32(rhs.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void jump_if_equal(Operand lhs, Operand rhs, Label& label)
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{
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cmp(lhs, rhs);
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// je label (RIP-relative 32-bit offset)
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emit8(0x0f);
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emit8(0x84);
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emit32(0xdeadbeef);
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label.add_jump(m_output.size());
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}
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void jump_if_not_equal(Operand lhs, Operand rhs, Label& label)
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{
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cmp(lhs, rhs);
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// jne label (RIP-relative 32-bit offset)
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emit8(0x0f);
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emit8(0x85);
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emit32(0xdeadbeef);
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label.add_jump(m_output.size());
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}
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void jump_if_less_than(Operand lhs, Operand rhs, Label& label)
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{
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cmp(lhs, rhs);
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// jl label (RIP-relative 32-bit offset)
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emit8(0x0f);
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emit8(0x8c);
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emit32(0xdeadbeef);
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label.add_jump(m_output.size());
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}
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void sign_extend_32_to_64_bits(Reg reg)
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{
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// movsxd (reg as 64-bit), (reg as 32-bit)
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emit8(0x48 | ((to_underlying(reg) >= 8) ? 1 << 0 : 0));
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emit8(0x63);
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emit8(0xc0 | (encode_reg(reg) << 3) | encode_reg(reg));
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}
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void bitwise_and(Operand dst, Operand src)
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{
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// and dst,src
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x21);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm32) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xe0 | encode_reg(dst.reg));
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void bitwise_or(Operand dst, Operand src)
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{
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// or dst,src
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x09);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm32) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xc8 | encode_reg(dst.reg));
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void enter()
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{
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push_callee_saved_registers();
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push(Operand::Register(Reg::RBP));
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mov(Operand::Register(Reg::RBP), Operand::Register(Reg::RSP));
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sub(Operand::Register(Reg::RSP), Operand::Imm8(8));
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}
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void exit()
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{
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// leave
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emit8(0xc9);
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pop_callee_saved_registers();
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// ret
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emit8(0xc3);
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}
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void push_callee_saved_registers()
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{
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// FIXME: Don't push RBX twice :^)
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push(Operand::Register(Reg::RBX));
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push(Operand::Register(Reg::RBX));
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push(Operand::Register(Reg::R12));
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push(Operand::Register(Reg::R13));
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push(Operand::Register(Reg::R14));
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push(Operand::Register(Reg::R15));
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}
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void pop_callee_saved_registers()
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{
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pop(Operand::Register(Reg::R15));
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pop(Operand::Register(Reg::R14));
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pop(Operand::Register(Reg::R13));
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pop(Operand::Register(Reg::R12));
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// FIXME: Don't pop RBX twice :^)
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pop(Operand::Register(Reg::RBX));
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pop(Operand::Register(Reg::RBX));
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}
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void push(Operand op)
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{
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if (op.type == Operand::Type::Reg) {
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if (to_underlying(op.reg) >= 8)
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emit8(0x49);
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emit8(0x50 | encode_reg(op.reg));
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} else if (op.type == Operand::Type::Imm32) {
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emit8(0x68);
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emit32(op.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void pop(Operand op)
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{
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if (op.type == Operand::Type::Reg) {
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if (to_underlying(op.reg) >= 8)
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emit8(0x49);
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emit8(0x58 | encode_reg(op.reg));
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void add(Operand dst, Operand src)
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{
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(dst.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(src.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x01);
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emit8(0xc0 | (encode_reg(dst.reg) << 3) | encode_reg(src.reg));
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm32) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xc0 | encode_reg(dst.reg));
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emit32(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm8) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xc0 | encode_reg(dst.reg));
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emit8(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void sub(Operand dst, Operand src)
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{
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(dst.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(src.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x29);
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emit8(0xc0 | (encode_reg(dst.reg) << 3) | encode_reg(src.reg));
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm32) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xe8 | encode_reg(dst.reg));
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emit32(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm8) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xe8 | encode_reg(dst.reg));
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emit8(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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}
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}
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void native_call(void* callee)
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{
|
||||
// push caller-saved registers on the stack
|
||||
// (callee-saved registers: RBX, RSP, RBP, and R12–R15)
|
||||
push(Operand::Register(Reg::RCX));
|
||||
push(Operand::Register(Reg::RDX));
|
||||
push(Operand::Register(Reg::RSI));
|
||||
push(Operand::Register(Reg::RDI));
|
||||
push(Operand::Register(Reg::R8));
|
||||
push(Operand::Register(Reg::R9));
|
||||
push(Operand::Register(Reg::R10));
|
||||
push(Operand::Register(Reg::R11));
|
||||
|
||||
// align the stack to 16-byte boundary
|
||||
sub(Operand::Register(Reg::RSP), Operand::Imm8(8));
|
||||
|
||||
// load callee into RAX
|
||||
mov(Operand::Register(Reg::RAX), Operand::Imm64(bit_cast<u64>(callee)));
|
||||
|
||||
// call RAX
|
||||
emit8(0xff);
|
||||
emit8(0xd0);
|
||||
|
||||
// adjust stack pointer
|
||||
add(Operand::Register(Reg::RSP), Operand::Imm8(8));
|
||||
|
||||
// restore caller-saved registers from the stack
|
||||
pop(Operand::Register(Reg::R11));
|
||||
pop(Operand::Register(Reg::R10));
|
||||
pop(Operand::Register(Reg::R9));
|
||||
pop(Operand::Register(Reg::R8));
|
||||
pop(Operand::Register(Reg::RDI));
|
||||
pop(Operand::Register(Reg::RSI));
|
||||
pop(Operand::Register(Reg::RDX));
|
||||
pop(Operand::Register(Reg::RCX));
|
||||
}
|
||||
|
||||
void trap()
|
||||
{
|
||||
// int3
|
||||
emit8(0xcc);
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue