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Everywhere: Rename ASSERT => VERIFY

Browse source 
(...and ASSERT_NOT_REACHED => VERIFY_NOT_REACHED)

Since all of these checks are done in release builds as well,
let's rename them to VERIFY to prevent confusion, as everyone is
used to assertions being compiled out in release.

We can introduce a new ASSERT macro that is specifically for debug
checks, but I'm doing this wholesale conversion first since we've
accumulated thousands of these already, and it's not immediately
obvious which ones are suitable for ASSERT.
This commit is contained in:
Andreas Kling 2021-02-23 20:42:32 +01:00
parent b33a6a443e
commit 5d180d1f99
725 changed files with 3448 additions and 3448 deletions
Download patch file Download diff file Expand all files Collapse all files

28
Kernel/Interrupts/APIC.cpp
View file

@ -142,13 +142,13 @@ bool APIC::initialized()
APIC& APIC::the()
{
ASSERT(APIC::initialized());
VERIFY(APIC::initialized());
return *s_apic;
}
UNMAP_AFTER_INIT void APIC::initialize()
{
ASSERT(!APIC::initialized());
VERIFY(!APIC::initialized());
s_apic.ensure_instance();
}
@ -302,7 +302,7 @@ UNMAP_AFTER_INIT bool APIC::init_bsp()
UNMAP_AFTER_INIT void APIC::do_boot_aps()
{
ASSERT(m_processor_enabled_cnt > 1);
VERIFY(m_processor_enabled_cnt > 1);
u32 aps_to_enable = m_processor_enabled_cnt - 1;
// Copy the APIC startup code and variables to P0x00008000
@ -326,7 +326,7 @@ UNMAP_AFTER_INIT void APIC::do_boot_aps()
// Store pointers to all stacks for the APs to use
auto ap_stack_array = APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_stacks);
ASSERT(aps_to_enable == apic_ap_stacks.size());
VERIFY(aps_to_enable == apic_ap_stacks.size());
for (size_t i = 0; i < aps_to_enable; i++) {
ap_stack_array[i] = apic_ap_stacks[i]->vaddr().get() + Thread::default_kernel_stack_size;
#if APIC_DEBUG
@ -429,7 +429,7 @@ UNMAP_AFTER_INIT void APIC::enable(u32 cpu)
}
// Use the CPU# as logical apic id
ASSERT(cpu <= 0xff);
VERIFY(cpu <= 0xff);
write_register(APIC_REG_LD, (read_register(APIC_REG_LD) & 0x00ffffff) | (cpu << 24)); // TODO: only if not in x2apic mode
// read it back to make sure it's actually set
@ -468,18 +468,18 @@ UNMAP_AFTER_INIT void APIC::enable(u32 cpu)
Thread* APIC::get_idle_thread(u32 cpu) const
{
ASSERT(cpu > 0);
VERIFY(cpu > 0);
return m_ap_idle_threads[cpu - 1];
}
UNMAP_AFTER_INIT void APIC::init_finished(u32 cpu)
{
// This method is called once the boot stack is no longer needed
ASSERT(cpu > 0);
ASSERT(cpu < m_processor_enabled_cnt);
VERIFY(cpu > 0);
VERIFY(cpu < m_processor_enabled_cnt);
// Since we're waiting on other APs here, we shouldn't have the
// scheduler lock
ASSERT(!g_scheduler_lock.own_lock());
VERIFY(!g_scheduler_lock.own_lock());
// Notify the BSP that we are done initializing. It will unmap the startup data at P8000
m_apic_ap_count.fetch_add(1, AK::MemoryOrder::memory_order_acq_rel);
@ -519,8 +519,8 @@ void APIC::send_ipi(u32 cpu)
#if APIC_SMP_DEBUG
klog() << "SMP: Send IPI from cpu #" << Processor::id() << " to cpu #" << cpu;
#endif
ASSERT(cpu != Processor::id());
ASSERT(cpu < 8);
VERIFY(cpu != Processor::id());
VERIFY(cpu < 8);
wait_for_pending_icr();
write_icr(ICRReg(IRQ_APIC_IPI + IRQ_VECTOR_BASE, ICRReg::Fixed, ICRReg::Logical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::NoShorthand, cpu));
}
@ -531,8 +531,8 @@ UNMAP_AFTER_INIT APICTimer* APIC::initialize_timers(HardwareTimerBase& calibrati
return nullptr;
// We should only initialize and calibrate the APIC timer once on the BSP!
ASSERT(Processor::id() == 0);
ASSERT(!m_apic_timer);
VERIFY(Processor::id() == 0);
VERIFY(!m_apic_timer);
m_apic_timer = APICTimer::initialize(IRQ_APIC_TIMER, calibration_timer);
return m_apic_timer;
@ -583,7 +583,7 @@ void APIC::setup_local_timer(u32 ticks, TimerMode timer_mode, bool enable)
config |= (1 << 3) | 2;
break;
default:
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
write_register(APIC_REG_TIMER_CONFIGURATION, config);

4
Kernel/Interrupts/GenericInterruptHandler.cpp
View file

@ -56,8 +56,8 @@ GenericInterruptHandler::~GenericInterruptHandler()
void GenericInterruptHandler::change_interrupt_number(u8 number)
{
ASSERT_INTERRUPTS_DISABLED();
ASSERT(!m_disable_remap);
VERIFY_INTERRUPTS_DISABLED();
VERIFY(!m_disable_remap);
unregister_generic_interrupt_handler(InterruptManagement::acquire_mapped_interrupt_number(interrupt_number()), *this);
m_interrupt_number = number;
register_generic_interrupt_handler(InterruptManagement::acquire_mapped_interrupt_number(interrupt_number()), *this);

44
Kernel/Interrupts/IOAPIC.cpp
View file

@ -80,7 +80,7 @@ void IOAPIC::map_interrupt_redirection(u8 interrupt_vector)
active_low = false;
break;
case 2:
ASSERT_NOT_REACHED(); // Reserved value
VERIFY_NOT_REACHED(); // Reserved value
case 3:
active_low = true;
break;
@ -96,7 +96,7 @@ void IOAPIC::map_interrupt_redirection(u8 interrupt_vector)
trigger_level_mode = false;
break;
case 2:
ASSERT_NOT_REACHED(); // Reserved value
VERIFY_NOT_REACHED(); // Reserved value
case 3:
trigger_level_mode = true;
break;
@ -127,8 +127,8 @@ bool IOAPIC::is_enabled() const
void IOAPIC::spurious_eoi(const GenericInterruptHandler& handler) const
{
InterruptDisabler disabler;
ASSERT(handler.type() == HandlerType::SpuriousInterruptHandler);
ASSERT(handler.interrupt_number() == APIC::spurious_interrupt_vector());
VERIFY(handler.type() == HandlerType::SpuriousInterruptHandler);
VERIFY(handler.interrupt_number() == APIC::spurious_interrupt_vector());
klog() << "IOAPIC::spurious_eoi - Spurious Interrupt occurred";
}
@ -148,7 +148,7 @@ void IOAPIC::map_isa_interrupts()
active_low = false;
break;
case 2:
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
case 3:
active_low = true;
break;
@ -164,7 +164,7 @@ void IOAPIC::map_isa_interrupts()
trigger_level_mode = false;
break;
case 2:
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
case 3:
trigger_level_mode = true;
break;
@ -196,7 +196,7 @@ void IOAPIC::reset_redirection_entry(int index) const
void IOAPIC::configure_redirection_entry(int index, u8 interrupt_vector, u8 delivery_mode, bool logical_destination, bool active_low, bool trigger_level_mode, bool masked, u8 destination) const
{
InterruptDisabler disabler;
ASSERT((u32)index < m_redirection_entries_count);
VERIFY((u32)index < m_redirection_entries_count);
u32 redirection_entry1 = interrupt_vector | (delivery_mode & 0b111) << 8 | logical_destination << 11 | active_low << 13 | trigger_level_mode << 15 | masked << 16;
u32 redirection_entry2 = destination << 24;
write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry1);
@ -219,7 +219,7 @@ void IOAPIC::mask_all_redirection_entries() const
void IOAPIC::mask_redirection_entry(u8 index) const
{
ASSERT((u32)index < m_redirection_entries_count);
VERIFY((u32)index < m_redirection_entries_count);
u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
if (redirection_entry & (1 << 16))
return;
@ -228,13 +228,13 @@ void IOAPIC::mask_redirection_entry(u8 index) const
bool IOAPIC::is_redirection_entry_masked(u8 index) const
{
ASSERT((u32)index < m_redirection_entries_count);
VERIFY((u32)index < m_redirection_entries_count);
return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & (1 << 16)) != 0;
}
void IOAPIC::unmask_redirection_entry(u8 index) const
{
ASSERT((u32)index < m_redirection_entries_count);
VERIFY((u32)index < m_redirection_entries_count);
u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
if (!(redirection_entry & (1 << 16)))
return;
@ -249,7 +249,7 @@ bool IOAPIC::is_vector_enabled(u8 interrupt_vector) const
u8 IOAPIC::read_redirection_entry_vector(u8 index) const
{
ASSERT((u32)index < m_redirection_entries_count);
VERIFY((u32)index < m_redirection_entries_count);
return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & 0xFF);
}
@ -266,52 +266,52 @@ Optional<int> IOAPIC::find_redirection_entry_by_vector(u8 vector) const
void IOAPIC::disable(const GenericInterruptHandler& handler)
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
VERIFY(!is_hard_disabled());
u8 interrupt_vector = handler.interrupt_number();
ASSERT(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
VERIFY(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
auto found_index = find_redirection_entry_by_vector(interrupt_vector);
if (!found_index.has_value()) {
map_interrupt_redirection(interrupt_vector);
found_index = find_redirection_entry_by_vector(interrupt_vector);
}
ASSERT(found_index.has_value());
VERIFY(found_index.has_value());
mask_redirection_entry(found_index.value());
}
void IOAPIC::enable(const GenericInterruptHandler& handler)
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
VERIFY(!is_hard_disabled());
u8 interrupt_vector = handler.interrupt_number();
ASSERT(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
VERIFY(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
auto found_index = find_redirection_entry_by_vector(interrupt_vector);
if (!found_index.has_value()) {
map_interrupt_redirection(interrupt_vector);
found_index = find_redirection_entry_by_vector(interrupt_vector);
}
ASSERT(found_index.has_value());
VERIFY(found_index.has_value());
unmask_redirection_entry(found_index.value());
}
void IOAPIC::eoi(const GenericInterruptHandler& handler) const
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
ASSERT(handler.type() != HandlerType::SpuriousInterruptHandler);
VERIFY(!is_hard_disabled());
VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
VERIFY(handler.type() != HandlerType::SpuriousInterruptHandler);
APIC::the().eoi();
}
u16 IOAPIC::get_isr() const
{
InterruptDisabler disabler;
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
u16 IOAPIC::get_irr() const
{
InterruptDisabler disabler;
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
void IOAPIC::write_register(u32 index, u32 value) const

2
Kernel/Interrupts/IRQHandler.cpp
View file

@ -46,7 +46,7 @@ bool IRQHandler::eoi()
{
dbgln_if(IRQ_DEBUG, "EOI IRQ {}", interrupt_number());
if (!m_shared_with_others) {
ASSERT(!m_responsible_irq_controller.is_null());
VERIFY(!m_responsible_irq_controller.is_null());
m_responsible_irq_controller->eoi(*this);
return true;
}

20
Kernel/Interrupts/InterruptManagement.cpp
View file

@ -52,13 +52,13 @@ bool InterruptManagement::initialized()
InterruptManagement& InterruptManagement::the()
{
ASSERT(InterruptManagement::initialized());
VERIFY(InterruptManagement::initialized());
return *s_interrupt_management;
}
UNMAP_AFTER_INIT void InterruptManagement::initialize()
{
ASSERT(!InterruptManagement::initialized());
VERIFY(!InterruptManagement::initialized());
s_interrupt_management = new InterruptManagement();
if (kernel_command_line().lookup("smp").value_or("off") == "on")
@ -78,8 +78,8 @@ void InterruptManagement::enumerate_interrupt_handlers(Function<void(GenericInte
IRQController& InterruptManagement::get_interrupt_controller(int index)
{
ASSERT(index >= 0);
ASSERT(!m_interrupt_controllers[index].is_null());
VERIFY(index >= 0);
VERIFY(!m_interrupt_controllers[index].is_null());
return *m_interrupt_controllers[index];
}
@ -94,7 +94,7 @@ u8 InterruptManagement::acquire_mapped_interrupt_number(u8 original_irq)
u8 InterruptManagement::acquire_irq_number(u8 mapped_interrupt_vector)
{
ASSERT(InterruptManagement::initialized());
VERIFY(InterruptManagement::initialized());
return InterruptManagement::the().get_irq_vector(mapped_interrupt_vector);
}
@ -102,7 +102,7 @@ u8 InterruptManagement::get_mapped_interrupt_vector(u8 original_irq)
{
// FIXME: For SMP configuration (with IOAPICs) use a better routing scheme to make redirections more efficient.
// FIXME: Find a better way to handle conflict with Syscall interrupt gate.
ASSERT((original_irq + IRQ_VECTOR_BASE) != syscall_vector);
VERIFY((original_irq + IRQ_VECTOR_BASE) != syscall_vector);
return original_irq;
}
@ -122,7 +122,7 @@ RefPtr<IRQController> InterruptManagement::get_responsible_irq_controller(u8 int
if (!irq_controller->is_hard_disabled())
return irq_controller;
}
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
UNMAP_AFTER_INIT PhysicalAddress InterruptManagement::search_for_madt()
@ -149,7 +149,7 @@ UNMAP_AFTER_INIT void InterruptManagement::switch_to_pic_mode()
SpuriousInterruptHandler::initialize(7);
SpuriousInterruptHandler::initialize(15);
for (auto& irq_controller : m_interrupt_controllers) {
ASSERT(irq_controller);
VERIFY(irq_controller);
if (irq_controller->type() == IRQControllerType::i82093AA) {
irq_controller->hard_disable();
dbgln("Interrupts: Detected {} - Disabled", irq_controller->model());
@ -180,7 +180,7 @@ UNMAP_AFTER_INIT void InterruptManagement::switch_to_ioapic_mode()
}
}
for (auto& irq_controller : m_interrupt_controllers) {
ASSERT(irq_controller);
VERIFY(irq_controller);
if (irq_controller->type() == IRQControllerType::i8259) {
irq_controller->hard_disable();
dbgln("Interrupts: Detected {} - Disabled", irq_controller->model());
@ -198,7 +198,7 @@ UNMAP_AFTER_INIT void InterruptManagement::switch_to_ioapic_mode()
UNMAP_AFTER_INIT void InterruptManagement::locate_apic_data()
{
ASSERT(!m_madt.is_null());
VERIFY(!m_madt.is_null());
auto madt = map_typed<ACPI::Structures::MADT>(m_madt);
int irq_controller_count = 0;

16
Kernel/Interrupts/PIC.cpp
View file

@ -69,8 +69,8 @@ bool PIC::is_enabled() const
void PIC::disable(const GenericInterruptHandler& handler)
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
VERIFY(!is_hard_disabled());
VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
u8 irq = handler.interrupt_number();
if (m_cached_irq_mask & (1 << irq))
return;
@ -94,7 +94,7 @@ UNMAP_AFTER_INIT PIC::PIC()
void PIC::spurious_eoi(const GenericInterruptHandler& handler) const
{
ASSERT(handler.type() == HandlerType::SpuriousInterruptHandler);
VERIFY(handler.type() == HandlerType::SpuriousInterruptHandler);
if (handler.interrupt_number() == 7)
return;
if (handler.interrupt_number() == 15) {
@ -111,15 +111,15 @@ bool PIC::is_vector_enabled(u8 irq) const
void PIC::enable(const GenericInterruptHandler& handler)
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
VERIFY(!is_hard_disabled());
VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
enable_vector(handler.interrupt_number());
}
void PIC::enable_vector(u8 irq)
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
VERIFY(!is_hard_disabled());
if (!(m_cached_irq_mask & (1 << irq)))
return;
u8 imr;
@ -138,9 +138,9 @@ void PIC::enable_vector(u8 irq)
void PIC::eoi(const GenericInterruptHandler& handler) const
{
InterruptDisabler disabler;
ASSERT(!is_hard_disabled());
VERIFY(!is_hard_disabled());
u8 irq = handler.interrupt_number();
ASSERT(irq >= gsi_base() && irq < interrupt_vectors_count());
VERIFY(irq >= gsi_base() && irq < interrupt_vectors_count());
if ((1 << irq) & m_cached_irq_mask) {
spurious_eoi(handler);
return;

4
Kernel/Interrupts/SharedIRQHandler.cpp
View file

@ -84,7 +84,7 @@ SharedIRQHandler::~SharedIRQHandler()
void SharedIRQHandler::handle_interrupt(const RegisterState& regs)
{
ASSERT_INTERRUPTS_DISABLED();
VERIFY_INTERRUPTS_DISABLED();
if constexpr (INTERRUPT_DEBUG) {
dbgln("Interrupt @ {}", interrupt_number());
@ -94,7 +94,7 @@ void SharedIRQHandler::handle_interrupt(const RegisterState& regs)
int i = 0;
for (auto* handler : m_handlers) {
dbgln_if(INTERRUPT_DEBUG, "Going for Interrupt Handling @ {}, Shared Interrupt {}", i, interrupt_number());
ASSERT(handler != nullptr);
VERIFY(handler != nullptr);
handler->increment_invoking_counter();
handler->handle_interrupt(regs);
dbgln_if(INTERRUPT_DEBUG, "Going for Interrupt Handling @ {}, Shared Interrupt {} - End", i, interrupt_number());

4
Kernel/Interrupts/SpuriousInterruptHandler.cpp
View file

@ -36,7 +36,7 @@ UNMAP_AFTER_INIT void SpuriousInterruptHandler::initialize(u8 interrupt_number)
void SpuriousInterruptHandler::register_handler(GenericInterruptHandler& handler)
{
ASSERT(!m_real_handler);
VERIFY(!m_real_handler);
m_real_handler = &handler;
}
void SpuriousInterruptHandler::unregister_handler(GenericInterruptHandler&)
@ -88,7 +88,7 @@ void SpuriousInterruptHandler::enable_interrupt_vector()
void SpuriousInterruptHandler::disable_interrupt_vector()
{
ASSERT(!m_real_irq); // this flag should not be set when we call this method
VERIFY(!m_real_irq); // this flag should not be set when we call this method
if (!m_enabled)
return;
m_enabled = false;

2
Kernel/Interrupts/UnhandledInterruptHandler.h
View file

@ -43,7 +43,7 @@ public:
virtual HandlerType type() const override { return HandlerType::UnhandledInterruptHandler; }
virtual const char* purpose() const override { return "Unhandled Interrupt Handler"; }
virtual const char* controller() const override { ASSERT_NOT_REACHED(); }
virtual const char* controller() const override { VERIFY_NOT_REACHED(); }
virtual size_t sharing_devices_count() const override { return 0; }
virtual bool is_shared_handler() const override { return false; }