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https://github.com/RGBCube/serenity
synced 2025-07-26 04:57:44 +00:00
Everywhere: Rename ASSERT => VERIFY
(...and ASSERT_NOT_REACHED => VERIFY_NOT_REACHED) Since all of these checks are done in release builds as well, let's rename them to VERIFY to prevent confusion, as everyone is used to assertions being compiled out in release. We can introduce a new ASSERT macro that is specifically for debug checks, but I'm doing this wholesale conversion first since we've accumulated thousands of these already, and it's not immediately obvious which ones are suitable for ASSERT.
This commit is contained in:
parent
b33a6a443e
commit
5d180d1f99
725 changed files with 3448 additions and 3448 deletions
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@ -142,13 +142,13 @@ bool APIC::initialized()
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APIC& APIC::the()
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{
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ASSERT(APIC::initialized());
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VERIFY(APIC::initialized());
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return *s_apic;
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}
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UNMAP_AFTER_INIT void APIC::initialize()
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{
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ASSERT(!APIC::initialized());
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VERIFY(!APIC::initialized());
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s_apic.ensure_instance();
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}
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@ -302,7 +302,7 @@ UNMAP_AFTER_INIT bool APIC::init_bsp()
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UNMAP_AFTER_INIT void APIC::do_boot_aps()
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{
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ASSERT(m_processor_enabled_cnt > 1);
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VERIFY(m_processor_enabled_cnt > 1);
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u32 aps_to_enable = m_processor_enabled_cnt - 1;
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// Copy the APIC startup code and variables to P0x00008000
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@ -326,7 +326,7 @@ UNMAP_AFTER_INIT void APIC::do_boot_aps()
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// Store pointers to all stacks for the APs to use
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auto ap_stack_array = APIC_INIT_VAR_PTR(u32, apic_startup_region->vaddr().as_ptr(), ap_cpu_init_stacks);
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ASSERT(aps_to_enable == apic_ap_stacks.size());
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VERIFY(aps_to_enable == apic_ap_stacks.size());
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for (size_t i = 0; i < aps_to_enable; i++) {
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ap_stack_array[i] = apic_ap_stacks[i]->vaddr().get() + Thread::default_kernel_stack_size;
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#if APIC_DEBUG
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@ -429,7 +429,7 @@ UNMAP_AFTER_INIT void APIC::enable(u32 cpu)
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}
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// Use the CPU# as logical apic id
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ASSERT(cpu <= 0xff);
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VERIFY(cpu <= 0xff);
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write_register(APIC_REG_LD, (read_register(APIC_REG_LD) & 0x00ffffff) | (cpu << 24)); // TODO: only if not in x2apic mode
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// read it back to make sure it's actually set
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@ -468,18 +468,18 @@ UNMAP_AFTER_INIT void APIC::enable(u32 cpu)
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Thread* APIC::get_idle_thread(u32 cpu) const
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{
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ASSERT(cpu > 0);
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VERIFY(cpu > 0);
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return m_ap_idle_threads[cpu - 1];
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}
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UNMAP_AFTER_INIT void APIC::init_finished(u32 cpu)
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{
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// This method is called once the boot stack is no longer needed
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ASSERT(cpu > 0);
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ASSERT(cpu < m_processor_enabled_cnt);
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VERIFY(cpu > 0);
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VERIFY(cpu < m_processor_enabled_cnt);
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// Since we're waiting on other APs here, we shouldn't have the
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// scheduler lock
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ASSERT(!g_scheduler_lock.own_lock());
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VERIFY(!g_scheduler_lock.own_lock());
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// Notify the BSP that we are done initializing. It will unmap the startup data at P8000
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m_apic_ap_count.fetch_add(1, AK::MemoryOrder::memory_order_acq_rel);
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@ -519,8 +519,8 @@ void APIC::send_ipi(u32 cpu)
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#if APIC_SMP_DEBUG
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klog() << "SMP: Send IPI from cpu #" << Processor::id() << " to cpu #" << cpu;
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#endif
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ASSERT(cpu != Processor::id());
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ASSERT(cpu < 8);
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VERIFY(cpu != Processor::id());
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VERIFY(cpu < 8);
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wait_for_pending_icr();
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write_icr(ICRReg(IRQ_APIC_IPI + IRQ_VECTOR_BASE, ICRReg::Fixed, ICRReg::Logical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::NoShorthand, cpu));
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}
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@ -531,8 +531,8 @@ UNMAP_AFTER_INIT APICTimer* APIC::initialize_timers(HardwareTimerBase& calibrati
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return nullptr;
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// We should only initialize and calibrate the APIC timer once on the BSP!
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ASSERT(Processor::id() == 0);
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ASSERT(!m_apic_timer);
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VERIFY(Processor::id() == 0);
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VERIFY(!m_apic_timer);
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m_apic_timer = APICTimer::initialize(IRQ_APIC_TIMER, calibration_timer);
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return m_apic_timer;
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@ -583,7 +583,7 @@ void APIC::setup_local_timer(u32 ticks, TimerMode timer_mode, bool enable)
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config |= (1 << 3) | 2;
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break;
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default:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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}
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write_register(APIC_REG_TIMER_CONFIGURATION, config);
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@ -56,8 +56,8 @@ GenericInterruptHandler::~GenericInterruptHandler()
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void GenericInterruptHandler::change_interrupt_number(u8 number)
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{
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ASSERT_INTERRUPTS_DISABLED();
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ASSERT(!m_disable_remap);
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VERIFY_INTERRUPTS_DISABLED();
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VERIFY(!m_disable_remap);
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unregister_generic_interrupt_handler(InterruptManagement::acquire_mapped_interrupt_number(interrupt_number()), *this);
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m_interrupt_number = number;
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register_generic_interrupt_handler(InterruptManagement::acquire_mapped_interrupt_number(interrupt_number()), *this);
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@ -80,7 +80,7 @@ void IOAPIC::map_interrupt_redirection(u8 interrupt_vector)
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active_low = false;
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break;
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case 2:
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ASSERT_NOT_REACHED(); // Reserved value
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VERIFY_NOT_REACHED(); // Reserved value
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case 3:
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active_low = true;
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break;
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@ -96,7 +96,7 @@ void IOAPIC::map_interrupt_redirection(u8 interrupt_vector)
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trigger_level_mode = false;
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break;
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case 2:
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ASSERT_NOT_REACHED(); // Reserved value
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VERIFY_NOT_REACHED(); // Reserved value
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case 3:
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trigger_level_mode = true;
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break;
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@ -127,8 +127,8 @@ bool IOAPIC::is_enabled() const
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void IOAPIC::spurious_eoi(const GenericInterruptHandler& handler) const
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{
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InterruptDisabler disabler;
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ASSERT(handler.type() == HandlerType::SpuriousInterruptHandler);
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ASSERT(handler.interrupt_number() == APIC::spurious_interrupt_vector());
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VERIFY(handler.type() == HandlerType::SpuriousInterruptHandler);
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VERIFY(handler.interrupt_number() == APIC::spurious_interrupt_vector());
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klog() << "IOAPIC::spurious_eoi - Spurious Interrupt occurred";
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}
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@ -148,7 +148,7 @@ void IOAPIC::map_isa_interrupts()
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active_low = false;
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break;
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case 2:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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case 3:
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active_low = true;
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break;
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@ -164,7 +164,7 @@ void IOAPIC::map_isa_interrupts()
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trigger_level_mode = false;
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break;
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case 2:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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case 3:
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trigger_level_mode = true;
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break;
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@ -196,7 +196,7 @@ void IOAPIC::reset_redirection_entry(int index) const
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void IOAPIC::configure_redirection_entry(int index, u8 interrupt_vector, u8 delivery_mode, bool logical_destination, bool active_low, bool trigger_level_mode, bool masked, u8 destination) const
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{
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InterruptDisabler disabler;
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ASSERT((u32)index < m_redirection_entries_count);
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VERIFY((u32)index < m_redirection_entries_count);
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u32 redirection_entry1 = interrupt_vector | (delivery_mode & 0b111) << 8 | logical_destination << 11 | active_low << 13 | trigger_level_mode << 15 | masked << 16;
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u32 redirection_entry2 = destination << 24;
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write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry1);
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@ -219,7 +219,7 @@ void IOAPIC::mask_all_redirection_entries() const
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void IOAPIC::mask_redirection_entry(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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VERIFY((u32)index < m_redirection_entries_count);
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u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
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if (redirection_entry & (1 << 16))
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return;
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@ -228,13 +228,13 @@ void IOAPIC::mask_redirection_entry(u8 index) const
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bool IOAPIC::is_redirection_entry_masked(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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VERIFY((u32)index < m_redirection_entries_count);
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return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & (1 << 16)) != 0;
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}
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void IOAPIC::unmask_redirection_entry(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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VERIFY((u32)index < m_redirection_entries_count);
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u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
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if (!(redirection_entry & (1 << 16)))
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return;
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@ -249,7 +249,7 @@ bool IOAPIC::is_vector_enabled(u8 interrupt_vector) const
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u8 IOAPIC::read_redirection_entry_vector(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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VERIFY((u32)index < m_redirection_entries_count);
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return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & 0xFF);
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}
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@ -266,52 +266,52 @@ Optional<int> IOAPIC::find_redirection_entry_by_vector(u8 vector) const
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void IOAPIC::disable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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VERIFY(!is_hard_disabled());
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u8 interrupt_vector = handler.interrupt_number();
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ASSERT(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
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VERIFY(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
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auto found_index = find_redirection_entry_by_vector(interrupt_vector);
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if (!found_index.has_value()) {
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map_interrupt_redirection(interrupt_vector);
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found_index = find_redirection_entry_by_vector(interrupt_vector);
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}
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ASSERT(found_index.has_value());
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VERIFY(found_index.has_value());
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mask_redirection_entry(found_index.value());
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}
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void IOAPIC::enable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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VERIFY(!is_hard_disabled());
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u8 interrupt_vector = handler.interrupt_number();
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ASSERT(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
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VERIFY(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
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auto found_index = find_redirection_entry_by_vector(interrupt_vector);
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if (!found_index.has_value()) {
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map_interrupt_redirection(interrupt_vector);
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found_index = find_redirection_entry_by_vector(interrupt_vector);
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}
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ASSERT(found_index.has_value());
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VERIFY(found_index.has_value());
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unmask_redirection_entry(found_index.value());
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}
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void IOAPIC::eoi(const GenericInterruptHandler& handler) const
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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ASSERT(handler.type() != HandlerType::SpuriousInterruptHandler);
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VERIFY(!is_hard_disabled());
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VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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VERIFY(handler.type() != HandlerType::SpuriousInterruptHandler);
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APIC::the().eoi();
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}
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u16 IOAPIC::get_isr() const
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{
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InterruptDisabler disabler;
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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}
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u16 IOAPIC::get_irr() const
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{
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InterruptDisabler disabler;
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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}
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void IOAPIC::write_register(u32 index, u32 value) const
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@ -46,7 +46,7 @@ bool IRQHandler::eoi()
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{
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dbgln_if(IRQ_DEBUG, "EOI IRQ {}", interrupt_number());
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if (!m_shared_with_others) {
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ASSERT(!m_responsible_irq_controller.is_null());
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VERIFY(!m_responsible_irq_controller.is_null());
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m_responsible_irq_controller->eoi(*this);
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return true;
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}
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@ -52,13 +52,13 @@ bool InterruptManagement::initialized()
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InterruptManagement& InterruptManagement::the()
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{
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ASSERT(InterruptManagement::initialized());
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VERIFY(InterruptManagement::initialized());
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return *s_interrupt_management;
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}
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UNMAP_AFTER_INIT void InterruptManagement::initialize()
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{
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ASSERT(!InterruptManagement::initialized());
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VERIFY(!InterruptManagement::initialized());
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s_interrupt_management = new InterruptManagement();
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if (kernel_command_line().lookup("smp").value_or("off") == "on")
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@ -78,8 +78,8 @@ void InterruptManagement::enumerate_interrupt_handlers(Function<void(GenericInte
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IRQController& InterruptManagement::get_interrupt_controller(int index)
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{
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ASSERT(index >= 0);
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ASSERT(!m_interrupt_controllers[index].is_null());
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VERIFY(index >= 0);
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VERIFY(!m_interrupt_controllers[index].is_null());
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return *m_interrupt_controllers[index];
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}
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@ -94,7 +94,7 @@ u8 InterruptManagement::acquire_mapped_interrupt_number(u8 original_irq)
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u8 InterruptManagement::acquire_irq_number(u8 mapped_interrupt_vector)
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{
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ASSERT(InterruptManagement::initialized());
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VERIFY(InterruptManagement::initialized());
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return InterruptManagement::the().get_irq_vector(mapped_interrupt_vector);
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}
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@ -102,7 +102,7 @@ u8 InterruptManagement::get_mapped_interrupt_vector(u8 original_irq)
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{
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// FIXME: For SMP configuration (with IOAPICs) use a better routing scheme to make redirections more efficient.
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// FIXME: Find a better way to handle conflict with Syscall interrupt gate.
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ASSERT((original_irq + IRQ_VECTOR_BASE) != syscall_vector);
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VERIFY((original_irq + IRQ_VECTOR_BASE) != syscall_vector);
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return original_irq;
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}
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@ -122,7 +122,7 @@ RefPtr<IRQController> InterruptManagement::get_responsible_irq_controller(u8 int
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if (!irq_controller->is_hard_disabled())
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return irq_controller;
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}
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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}
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UNMAP_AFTER_INIT PhysicalAddress InterruptManagement::search_for_madt()
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@ -149,7 +149,7 @@ UNMAP_AFTER_INIT void InterruptManagement::switch_to_pic_mode()
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SpuriousInterruptHandler::initialize(7);
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SpuriousInterruptHandler::initialize(15);
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for (auto& irq_controller : m_interrupt_controllers) {
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ASSERT(irq_controller);
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VERIFY(irq_controller);
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if (irq_controller->type() == IRQControllerType::i82093AA) {
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irq_controller->hard_disable();
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dbgln("Interrupts: Detected {} - Disabled", irq_controller->model());
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@ -180,7 +180,7 @@ UNMAP_AFTER_INIT void InterruptManagement::switch_to_ioapic_mode()
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}
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}
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for (auto& irq_controller : m_interrupt_controllers) {
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ASSERT(irq_controller);
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VERIFY(irq_controller);
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if (irq_controller->type() == IRQControllerType::i8259) {
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irq_controller->hard_disable();
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dbgln("Interrupts: Detected {} - Disabled", irq_controller->model());
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@ -198,7 +198,7 @@ UNMAP_AFTER_INIT void InterruptManagement::switch_to_ioapic_mode()
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UNMAP_AFTER_INIT void InterruptManagement::locate_apic_data()
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{
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ASSERT(!m_madt.is_null());
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VERIFY(!m_madt.is_null());
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auto madt = map_typed<ACPI::Structures::MADT>(m_madt);
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int irq_controller_count = 0;
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@ -69,8 +69,8 @@ bool PIC::is_enabled() const
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void PIC::disable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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VERIFY(!is_hard_disabled());
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VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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u8 irq = handler.interrupt_number();
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if (m_cached_irq_mask & (1 << irq))
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return;
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@ -94,7 +94,7 @@ UNMAP_AFTER_INIT PIC::PIC()
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void PIC::spurious_eoi(const GenericInterruptHandler& handler) const
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{
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ASSERT(handler.type() == HandlerType::SpuriousInterruptHandler);
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VERIFY(handler.type() == HandlerType::SpuriousInterruptHandler);
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if (handler.interrupt_number() == 7)
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return;
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if (handler.interrupt_number() == 15) {
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@ -111,15 +111,15 @@ bool PIC::is_vector_enabled(u8 irq) const
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void PIC::enable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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VERIFY(!is_hard_disabled());
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VERIFY(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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enable_vector(handler.interrupt_number());
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}
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void PIC::enable_vector(u8 irq)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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VERIFY(!is_hard_disabled());
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if (!(m_cached_irq_mask & (1 << irq)))
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return;
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u8 imr;
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@ -138,9 +138,9 @@ void PIC::enable_vector(u8 irq)
|
|||
void PIC::eoi(const GenericInterruptHandler& handler) const
|
||||
{
|
||||
InterruptDisabler disabler;
|
||||
ASSERT(!is_hard_disabled());
|
||||
VERIFY(!is_hard_disabled());
|
||||
u8 irq = handler.interrupt_number();
|
||||
ASSERT(irq >= gsi_base() && irq < interrupt_vectors_count());
|
||||
VERIFY(irq >= gsi_base() && irq < interrupt_vectors_count());
|
||||
if ((1 << irq) & m_cached_irq_mask) {
|
||||
spurious_eoi(handler);
|
||||
return;
|
||||
|
|
|
@ -84,7 +84,7 @@ SharedIRQHandler::~SharedIRQHandler()
|
|||
|
||||
void SharedIRQHandler::handle_interrupt(const RegisterState& regs)
|
||||
{
|
||||
ASSERT_INTERRUPTS_DISABLED();
|
||||
VERIFY_INTERRUPTS_DISABLED();
|
||||
|
||||
if constexpr (INTERRUPT_DEBUG) {
|
||||
dbgln("Interrupt @ {}", interrupt_number());
|
||||
|
@ -94,7 +94,7 @@ void SharedIRQHandler::handle_interrupt(const RegisterState& regs)
|
|||
int i = 0;
|
||||
for (auto* handler : m_handlers) {
|
||||
dbgln_if(INTERRUPT_DEBUG, "Going for Interrupt Handling @ {}, Shared Interrupt {}", i, interrupt_number());
|
||||
ASSERT(handler != nullptr);
|
||||
VERIFY(handler != nullptr);
|
||||
handler->increment_invoking_counter();
|
||||
handler->handle_interrupt(regs);
|
||||
dbgln_if(INTERRUPT_DEBUG, "Going for Interrupt Handling @ {}, Shared Interrupt {} - End", i, interrupt_number());
|
||||
|
|
|
@ -36,7 +36,7 @@ UNMAP_AFTER_INIT void SpuriousInterruptHandler::initialize(u8 interrupt_number)
|
|||
|
||||
void SpuriousInterruptHandler::register_handler(GenericInterruptHandler& handler)
|
||||
{
|
||||
ASSERT(!m_real_handler);
|
||||
VERIFY(!m_real_handler);
|
||||
m_real_handler = &handler;
|
||||
}
|
||||
void SpuriousInterruptHandler::unregister_handler(GenericInterruptHandler&)
|
||||
|
@ -88,7 +88,7 @@ void SpuriousInterruptHandler::enable_interrupt_vector()
|
|||
|
||||
void SpuriousInterruptHandler::disable_interrupt_vector()
|
||||
{
|
||||
ASSERT(!m_real_irq); // this flag should not be set when we call this method
|
||||
VERIFY(!m_real_irq); // this flag should not be set when we call this method
|
||||
if (!m_enabled)
|
||||
return;
|
||||
m_enabled = false;
|
||||
|
|
|
@ -43,7 +43,7 @@ public:
|
|||
|
||||
virtual HandlerType type() const override { return HandlerType::UnhandledInterruptHandler; }
|
||||
virtual const char* purpose() const override { return "Unhandled Interrupt Handler"; }
|
||||
virtual const char* controller() const override { ASSERT_NOT_REACHED(); }
|
||||
virtual const char* controller() const override { VERIFY_NOT_REACHED(); }
|
||||
|
||||
virtual size_t sharing_devices_count() const override { return 0; }
|
||||
virtual bool is_shared_handler() const override { return false; }
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue