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Everywhere: Rename ASSERT => VERIFY

Browse source 
(...and ASSERT_NOT_REACHED => VERIFY_NOT_REACHED)

Since all of these checks are done in release builds as well,
let's rename them to VERIFY to prevent confusion, as everyone is
used to assertions being compiled out in release.

We can introduce a new ASSERT macro that is specifically for debug
checks, but I'm doing this wholesale conversion first since we've
accumulated thousands of these already, and it's not immediately
obvious which ones are suitable for ASSERT.
This commit is contained in:
Andreas Kling 2021-02-23 20:42:32 +01:00
parent b33a6a443e
commit 5d180d1f99
725 changed files with 3448 additions and 3448 deletions
Download patch file Download diff file Expand all files Collapse all files

28
Userland/DevTools/UserspaceEmulator/Emulator.cpp
View file

@ -70,7 +70,7 @@ static Emulator* s_the;
Emulator& Emulator::the()
{
ASSERT(s_the);
VERIFY(s_the);
return *s_the;
}
@ -95,7 +95,7 @@ Emulator::Emulator(const String& executable_path, const Vector<String>& argument
m_range_allocator.initialize_with_range(VirtualAddress(base), userspace_range_ceiling - base);
ASSERT(!s_the);
VERIFY(!s_the);
s_the = this;
// setup_stack(arguments, environment);
register_signal_handlers();
@ -190,7 +190,7 @@ bool Emulator::load_elf()
if (!executable_elf.is_dynamic()) {
// FIXME: Support static objects
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
String interpreter_path;
@ -199,18 +199,18 @@ bool Emulator::load_elf()
return false;
}
ASSERT(!interpreter_path.is_null());
VERIFY(!interpreter_path.is_null());
dbgln("interpreter: {}", interpreter_path);
auto interpreter_file_or_error = MappedFile::map(interpreter_path);
ASSERT(!interpreter_file_or_error.is_error());
VERIFY(!interpreter_file_or_error.is_error());
auto interpreter_image_data = interpreter_file_or_error.value()->bytes();
ELF::Image interpreter_image(interpreter_image_data);
constexpr FlatPtr interpreter_load_offset = 0x08000000;
interpreter_image.for_each_program_header([&](const ELF::Image::ProgramHeader& program_header) {
// Loader is not allowed to have its own TLS regions
ASSERT(program_header.type() != PT_TLS);
VERIFY(program_header.type() != PT_TLS);
if (program_header.type() == PT_LOAD) {
auto region = make<SimpleRegion>(program_header.vaddr().offset(interpreter_load_offset).get(), program_header.size_in_memory());
@ -983,7 +983,7 @@ int Emulator::virt$pipe(FlatPtr vm_pipefd, int flags)
u32 Emulator::virt$munmap(FlatPtr address, u32 size)
{
auto* region = mmu().find_region({ 0x23, address });
ASSERT(region);
VERIFY(region);
if (region->size() != round_up_to_power_of_two(size, PAGE_SIZE))
TODO();
m_range_allocator.deallocate(region->range());
@ -1024,7 +1024,7 @@ u32 Emulator::virt$mmap(u32 params_addr)
auto region = MmapRegion::create_file_backed(final_address, final_size, params.prot, params.flags, params.fd, params.offset, name_str);
if (region->name() == "libc.so: .text (Emulated)") {
bool rc = find_malloc_symbols(*region);
ASSERT(rc);
VERIFY(rc);
}
mmu().add_region(move(region));
}
@ -1040,7 +1040,7 @@ FlatPtr Emulator::virt$mremap(FlatPtr params_addr)
if (auto* region = mmu().find_region({ m_cpu.ds(), params.old_address })) {
if (!is<MmapRegion>(*region))
return -EINVAL;
ASSERT(region->size() == params.old_size);
VERIFY(region->size() == params.old_size);
auto& mmap_region = *(MmapRegion*)region;
auto* ptr = mremap(mmap_region.data(), mmap_region.size(), mmap_region.size(), params.flags);
if (ptr == MAP_FAILED)
@ -1089,7 +1089,7 @@ u32 Emulator::virt$mprotect(FlatPtr base, size_t size, int prot)
if (auto* region = mmu().find_region({ m_cpu.ds(), base })) {
if (!is<MmapRegion>(*region))
return -EINVAL;
ASSERT(region->size() == size);
VERIFY(region->size() == size);
auto& mmap_region = *(MmapRegion*)region;
mmap_region.set_prot(prot);
return 0;
@ -1420,7 +1420,7 @@ enum class DefaultSignalAction {
static DefaultSignalAction default_signal_action(int signal)
{
ASSERT(signal && signal < NSIG);
VERIFY(signal && signal < NSIG);
switch (signal) {
case SIGHUP:
@ -1460,7 +1460,7 @@ static DefaultSignalAction default_signal_action(int signal)
case SIGTTOU:
return DefaultSignalAction::Stop;
}
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
void Emulator::dispatch_one_pending_signal()
@ -1471,7 +1471,7 @@ void Emulator::dispatch_one_pending_signal()
if (m_pending_signals & mask)
break;
}
ASSERT(signum != -1);
VERIFY(signum != -1);
m_pending_signals &= ~(1 << signum);
auto& handler = m_signal_handler[signum];
@ -1516,7 +1516,7 @@ void Emulator::dispatch_one_pending_signal()
m_cpu.push32(shadow_wrap_as_initialized(handler.handler));
m_cpu.push32(shadow_wrap_as_initialized(0u));
ASSERT((m_cpu.esp().value() % 16) == 0);
VERIFY((m_cpu.esp().value() % 16) == 0);
m_cpu.set_eip(m_signal_trampoline);
}

20
Userland/DevTools/UserspaceEmulator/MallocTracer.cpp
View file

@ -60,8 +60,8 @@ void MallocTracer::target_did_malloc(Badge<SoftCPU>, FlatPtr address, size_t siz
if (m_emulator.is_in_loader_code())
return;
auto* region = m_emulator.mmu().find_region({ 0x23, address });
ASSERT(region);
ASSERT(is<MmapRegion>(*region));
VERIFY(region);
VERIFY(is<MmapRegion>(*region));
auto& mmap_region = static_cast<MmapRegion&>(*region);
// Mark the containing mmap region as a malloc block!
@ -71,7 +71,7 @@ void MallocTracer::target_did_malloc(Badge<SoftCPU>, FlatPtr address, size_t siz
memset(shadow_bits, 0, size);
if (auto* existing_mallocation = find_mallocation(address)) {
ASSERT(existing_mallocation->freed);
VERIFY(existing_mallocation->freed);
existing_mallocation->size = size;
existing_mallocation->freed = false;
existing_mallocation->malloc_backtrace = m_emulator.raw_backtrace();
@ -110,7 +110,7 @@ ALWAYS_INLINE size_t MallocRegionMetadata::chunk_index_for_address(FlatPtr addre
return 0;
}
auto chunk_offset = address - (this->address + sizeof(ChunkedBlock));
ASSERT(this->chunk_size);
VERIFY(this->chunk_size);
return chunk_offset / this->chunk_size;
}
@ -143,15 +143,15 @@ void MallocTracer::target_did_realloc(Badge<SoftCPU>, FlatPtr address, size_t si
if (m_emulator.is_in_loader_code())
return;
auto* region = m_emulator.mmu().find_region({ 0x23, address });
ASSERT(region);
ASSERT(is<MmapRegion>(*region));
VERIFY(region);
VERIFY(is<MmapRegion>(*region));
auto& mmap_region = static_cast<MmapRegion&>(*region);
ASSERT(mmap_region.is_malloc_block());
VERIFY(mmap_region.is_malloc_block());
auto* existing_mallocation = find_mallocation(address);
ASSERT(existing_mallocation);
ASSERT(!existing_mallocation->freed);
VERIFY(existing_mallocation);
VERIFY(!existing_mallocation->freed);
size_t old_size = existing_mallocation->size;
@ -296,7 +296,7 @@ void MallocTracer::audit_write(const Region& region, FlatPtr address, size_t siz
bool MallocTracer::is_reachable(const Mallocation& mallocation) const
{
ASSERT(!mallocation.freed);
VERIFY(!mallocation.freed);
bool reachable = false;

2
Userland/DevTools/UserspaceEmulator/MallocTracer.h
View file

@ -105,7 +105,7 @@ ALWAYS_INLINE Mallocation* MallocTracer::find_mallocation(const Region& region,
auto& mallocation = malloc_data->mallocation_for_address(address);
if (!mallocation.used)
return nullptr;
ASSERT(mallocation.contains(address));
VERIFY(mallocation.contains(address));
return &mallocation;
}

22
Userland/DevTools/UserspaceEmulator/MmapRegion.cpp
View file

@ -48,7 +48,7 @@ NonnullOwnPtr<MmapRegion> MmapRegion::create_file_backed(u32 base, u32 size, u32
region->m_name = name;
}
region->m_data = (u8*)mmap_with_name(nullptr, size, prot, flags, fd, offset, name.is_empty() ? nullptr : name.characters());
ASSERT(region->m_data != MAP_FAILED);
VERIFY(region->m_data != MAP_FAILED);
return region;
}
@ -82,7 +82,7 @@ ValueWithShadow<u8> MmapRegion::read8(FlatPtr offset)
tracer->audit_read(*this, base() + offset, 1);
}
ASSERT(offset < size());
VERIFY(offset < size());
return { *reinterpret_cast<const u8*>(m_data + offset), *reinterpret_cast<const u8*>(m_shadow_data + offset) };
}
@ -99,7 +99,7 @@ ValueWithShadow<u16> MmapRegion::read16(u32 offset)
tracer->audit_read(*this, base() + offset, 2);
}
ASSERT(offset + 1 < size());
VERIFY(offset + 1 < size());
return { *reinterpret_cast<const u16*>(m_data + offset), *reinterpret_cast<const u16*>(m_shadow_data + offset) };
}
@ -116,7 +116,7 @@ ValueWithShadow<u32> MmapRegion::read32(u32 offset)
tracer->audit_read(*this, base() + offset, 4);
}
ASSERT(offset + 3 < size());
VERIFY(offset + 3 < size());
return { *reinterpret_cast<const u32*>(m_data + offset), *reinterpret_cast<const u32*>(m_shadow_data + offset) };
}
@ -133,7 +133,7 @@ ValueWithShadow<u64> MmapRegion::read64(u32 offset)
tracer->audit_read(*this, base() + offset, 8);
}
ASSERT(offset + 7 < size());
VERIFY(offset + 7 < size());
return { *reinterpret_cast<const u64*>(m_data + offset), *reinterpret_cast<const u64*>(m_shadow_data + offset) };
}
@ -150,7 +150,7 @@ void MmapRegion::write8(u32 offset, ValueWithShadow<u8> value)
tracer->audit_write(*this, base() + offset, 1);
}
ASSERT(offset < size());
VERIFY(offset < size());
*reinterpret_cast<u8*>(m_data + offset) = value.value();
*reinterpret_cast<u8*>(m_shadow_data + offset) = value.shadow();
}
@ -168,7 +168,7 @@ void MmapRegion::write16(u32 offset, ValueWithShadow<u16> value)
tracer->audit_write(*this, base() + offset, 2);
}
ASSERT(offset + 1 < size());
VERIFY(offset + 1 < size());
*reinterpret_cast<u16*>(m_data + offset) = value.value();
*reinterpret_cast<u16*>(m_shadow_data + offset) = value.shadow();
}
@ -186,8 +186,8 @@ void MmapRegion::write32(u32 offset, ValueWithShadow<u32> value)
tracer->audit_write(*this, base() + offset, 4);
}
ASSERT(offset + 3 < size());
ASSERT(m_data != m_shadow_data);
VERIFY(offset + 3 < size());
VERIFY(m_data != m_shadow_data);
*reinterpret_cast<u32*>(m_data + offset) = value.value();
*reinterpret_cast<u32*>(m_shadow_data + offset) = value.shadow();
}
@ -205,8 +205,8 @@ void MmapRegion::write64(u32 offset, ValueWithShadow<u64> value)
tracer->audit_write(*this, base() + offset, 8);
}
ASSERT(offset + 7 < size());
ASSERT(m_data != m_shadow_data);
VERIFY(offset + 7 < size());
VERIFY(m_data != m_shadow_data);
*reinterpret_cast<u64*>(m_data + offset) = value.value();
*reinterpret_cast<u64*>(m_shadow_data + offset) = value.shadow();
}

2
Userland/DevTools/UserspaceEmulator/Range.cpp
View file

@ -31,7 +31,7 @@ namespace UserspaceEmulator {
Vector<Range, 2> Range::carve(const Range& taken)
{
ASSERT((taken.size() % PAGE_SIZE) == 0);
VERIFY((taken.size() % PAGE_SIZE) == 0);
Vector<Range, 2> parts;
if (taken == *this)
return {};

32
Userland/DevTools/UserspaceEmulator/RangeAllocator.cpp
View file

@ -61,11 +61,11 @@ void RangeAllocator::dump() const
void RangeAllocator::carve_at_index(int index, const Range& range)
{
auto remaining_parts = m_available_ranges[index].carve(range);
ASSERT(remaining_parts.size() >= 1);
ASSERT(m_total_range.contains(remaining_parts[0]));
VERIFY(remaining_parts.size() >= 1);
VERIFY(m_total_range.contains(remaining_parts[0]));
m_available_ranges[index] = remaining_parts[0];
if (remaining_parts.size() == 2) {
ASSERT(m_total_range.contains(remaining_parts[1]));
VERIFY(m_total_range.contains(remaining_parts[1]));
m_available_ranges.insert(index + 1, move(remaining_parts[1]));
}
}
@ -75,8 +75,8 @@ Optional<Range> RangeAllocator::allocate_randomized(size_t size, size_t alignmen
if (!size)
return {};
ASSERT((size % PAGE_SIZE) == 0);
ASSERT((alignment % PAGE_SIZE) == 0);
VERIFY((size % PAGE_SIZE) == 0);
VERIFY((alignment % PAGE_SIZE) == 0);
// FIXME: I'm sure there's a smarter way to do this.
static constexpr size_t maximum_randomization_attempts = 1000;
@ -100,8 +100,8 @@ Optional<Range> RangeAllocator::allocate_anywhere(size_t size, size_t alignment)
if (!size)
return {};
ASSERT((size % PAGE_SIZE) == 0);
ASSERT((alignment % PAGE_SIZE) == 0);
VERIFY((size % PAGE_SIZE) == 0);
VERIFY((alignment % PAGE_SIZE) == 0);
#ifdef VM_GUARD_PAGES
// NOTE: We pad VM allocations with a guard page on each side.
@ -128,7 +128,7 @@ Optional<Range> RangeAllocator::allocate_anywhere(size_t size, size_t alignment)
FlatPtr aligned_base = round_up_to_power_of_two(initial_base, alignment);
Range allocated_range(VirtualAddress(aligned_base), size);
ASSERT(m_total_range.contains(allocated_range));
VERIFY(m_total_range.contains(allocated_range));
if (available_range == allocated_range) {
m_available_ranges.remove(i);
@ -146,13 +146,13 @@ Optional<Range> RangeAllocator::allocate_specific(VirtualAddress base, size_t si
if (!size)
return {};
ASSERT(base.is_page_aligned());
ASSERT((size % PAGE_SIZE) == 0);
VERIFY(base.is_page_aligned());
VERIFY((size % PAGE_SIZE) == 0);
Range allocated_range(base, size);
for (size_t i = 0; i < m_available_ranges.size(); ++i) {
auto& available_range = m_available_ranges[i];
ASSERT(m_total_range.contains(allocated_range));
VERIFY(m_total_range.contains(allocated_range));
if (!available_range.contains(base, size))
continue;
if (available_range == allocated_range) {
@ -167,11 +167,11 @@ Optional<Range> RangeAllocator::allocate_specific(VirtualAddress base, size_t si
void RangeAllocator::deallocate(const Range& range)
{
ASSERT(m_total_range.contains(range));
ASSERT(range.size());
ASSERT((range.size() % PAGE_SIZE) == 0);
ASSERT(range.base() < range.end());
ASSERT(!m_available_ranges.is_empty());
VERIFY(m_total_range.contains(range));
VERIFY(range.size());
VERIFY((range.size() % PAGE_SIZE) == 0);
VERIFY(range.base() < range.end());
VERIFY(!m_available_ranges.is_empty());
size_t nearby_index = 0;
auto* existing_range = binary_search(

16
Userland/DevTools/UserspaceEmulator/SimpleRegion.cpp
View file

@ -45,52 +45,52 @@ SimpleRegion::~SimpleRegion()
ValueWithShadow<u8> SimpleRegion::read8(FlatPtr offset)
{
ASSERT(offset < size());
VERIFY(offset < size());
return { *reinterpret_cast<const u8*>(m_data + offset), *reinterpret_cast<const u8*>(m_shadow_data + offset) };
}
ValueWithShadow<u16> SimpleRegion::read16(u32 offset)
{
ASSERT(offset + 1 < size());
VERIFY(offset + 1 < size());
return { *reinterpret_cast<const u16*>(m_data + offset), *reinterpret_cast<const u16*>(m_shadow_data + offset) };
}
ValueWithShadow<u32> SimpleRegion::read32(u32 offset)
{
ASSERT(offset + 3 < size());
VERIFY(offset + 3 < size());
return { *reinterpret_cast<const u32*>(m_data + offset), *reinterpret_cast<const u32*>(m_shadow_data + offset) };
}
ValueWithShadow<u64> SimpleRegion::read64(u32 offset)
{
ASSERT(offset + 7 < size());
VERIFY(offset + 7 < size());
return { *reinterpret_cast<const u64*>(m_data + offset), *reinterpret_cast<const u64*>(m_shadow_data + offset) };
}
void SimpleRegion::write8(u32 offset, ValueWithShadow<u8> value)
{
ASSERT(offset < size());
VERIFY(offset < size());
*reinterpret_cast<u8*>(m_data + offset) = value.value();
*reinterpret_cast<u8*>(m_shadow_data + offset) = value.shadow();
}
void SimpleRegion::write16(u32 offset, ValueWithShadow<u16> value)
{
ASSERT(offset + 1 < size());
VERIFY(offset + 1 < size());
*reinterpret_cast<u16*>(m_data + offset) = value.value();
*reinterpret_cast<u16*>(m_shadow_data + offset) = value.shadow();
}
void SimpleRegion::write32(u32 offset, ValueWithShadow<u32> value)
{
ASSERT(offset + 3 < size());
VERIFY(offset + 3 < size());
*reinterpret_cast<u32*>(m_data + offset) = value.value();
*reinterpret_cast<u32*>(m_shadow_data + offset) = value.shadow();
}
void SimpleRegion::write64(u32 offset, ValueWithShadow<u64> value)
{
ASSERT(offset + 7 < size());
VERIFY(offset + 7 < size());
*reinterpret_cast<u64*>(m_data + offset) = value.value();
*reinterpret_cast<u64*>(m_shadow_data + offset) = value.shadow();
}

100
Userland/DevTools/UserspaceEmulator/SoftCPU.cpp
View file

@ -124,14 +124,14 @@ void SoftCPU::did_receive_secret_data()
if (auto* tracer = m_emulator.malloc_tracer())
tracer->target_did_realloc({}, m_secret_data[2], m_secret_data[1]);
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
}
void SoftCPU::update_code_cache()
{
auto* region = m_emulator.mmu().find_region({ cs(), eip() });
ASSERT(region);
VERIFY(region);
if (!region->is_executable()) {
reportln("SoftCPU::update_code_cache: Non-executable region @ {:p}", eip());
@ -146,7 +146,7 @@ void SoftCPU::update_code_cache()
ValueWithShadow<u8> SoftCPU::read_memory8(X86::LogicalAddress address)
{
ASSERT(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
auto value = m_emulator.mmu().read8(address);
#if MEMORY_DEBUG
outln("\033[36;1mread_memory8: @{:04x}:{:08x} -> {:02x} ({:02x})\033[0m", address.selector(), address.offset(), value, value.shadow());
@ -156,7 +156,7 @@ ValueWithShadow<u8> SoftCPU::read_memory8(X86::LogicalAddress address)
ValueWithShadow<u16> SoftCPU::read_memory16(X86::LogicalAddress address)
{
ASSERT(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
auto value = m_emulator.mmu().read16(address);
#if MEMORY_DEBUG
outln("\033[36;1mread_memory16: @{:04x}:{:08x} -> {:04x} ({:04x})\033[0m", address.selector(), address.offset(), value, value.shadow());
@ -166,7 +166,7 @@ ValueWithShadow<u16> SoftCPU::read_memory16(X86::LogicalAddress address)
ValueWithShadow<u32> SoftCPU::read_memory32(X86::LogicalAddress address)
{
ASSERT(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
auto value = m_emulator.mmu().read32(address);
#if MEMORY_DEBUG
outln("\033[36;1mread_memory32: @{:04x}:{:08x} -> {:08x} ({:08x})\033[0m", address.selector(), address.offset(), value, value.shadow());
@ -176,7 +176,7 @@ ValueWithShadow<u32> SoftCPU::read_memory32(X86::LogicalAddress address)
ValueWithShadow<u64> SoftCPU::read_memory64(X86::LogicalAddress address)
{
ASSERT(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x1b || address.selector() == 0x23 || address.selector() == 0x2b);
auto value = m_emulator.mmu().read64(address);
#if MEMORY_DEBUG
outln("\033[36;1mread_memory64: @{:04x}:{:08x} -> {:016x} ({:016x})\033[0m", address.selector(), address.offset(), value, value.shadow());
@ -186,7 +186,7 @@ ValueWithShadow<u64> SoftCPU::read_memory64(X86::LogicalAddress address)
void SoftCPU::write_memory8(X86::LogicalAddress address, ValueWithShadow<u8> value)
{
ASSERT(address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x23 || address.selector() == 0x2b);
#if MEMORY_DEBUG
outln("\033[36;1mwrite_memory8: @{:04x}:{:08x} <- {:02x} ({:02x})\033[0m", address.selector(), address.offset(), value, value.shadow());
#endif
@ -195,7 +195,7 @@ void SoftCPU::write_memory8(X86::LogicalAddress address, ValueWithShadow<u8> val
void SoftCPU::write_memory16(X86::LogicalAddress address, ValueWithShadow<u16> value)
{
ASSERT(address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x23 || address.selector() == 0x2b);
#if MEMORY_DEBUG
outln("\033[36;1mwrite_memory16: @{:04x}:{:08x} <- {:04x} ({:04x})\033[0m", address.selector(), address.offset(), value, value.shadow());
#endif
@ -204,7 +204,7 @@ void SoftCPU::write_memory16(X86::LogicalAddress address, ValueWithShadow<u16> v
void SoftCPU::write_memory32(X86::LogicalAddress address, ValueWithShadow<u32> value)
{
ASSERT(address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x23 || address.selector() == 0x2b);
#if MEMORY_DEBUG
outln("\033[36;1mwrite_memory32: @{:04x}:{:08x} <- {:08x} ({:08x})\033[0m", address.selector(), address.offset(), value, value.shadow());
#endif
@ -213,7 +213,7 @@ void SoftCPU::write_memory32(X86::LogicalAddress address, ValueWithShadow<u32> v
void SoftCPU::write_memory64(X86::LogicalAddress address, ValueWithShadow<u64> value)
{
ASSERT(address.selector() == 0x23 || address.selector() == 0x2b);
VERIFY(address.selector() == 0x23 || address.selector() == 0x2b);
#if MEMORY_DEBUG
outln("\033[36;1mwrite_memory64: @{:04x}:{:08x} <- {:016x} ({:016x})\033[0m", address.selector(), address.offset(), value, value.shadow());
#endif
@ -363,7 +363,7 @@ ALWAYS_INLINE static T op_xor(SoftCPU& cpu, const T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -395,7 +395,7 @@ ALWAYS_INLINE static T op_or(SoftCPU& cpu, const T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -427,7 +427,7 @@ ALWAYS_INLINE static T op_sub(SoftCPU& cpu, const T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -464,7 +464,7 @@ ALWAYS_INLINE static T op_sbb_impl(SoftCPU& cpu, const T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -505,7 +505,7 @@ ALWAYS_INLINE static T op_add(SoftCPU& cpu, T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -542,7 +542,7 @@ ALWAYS_INLINE static T op_adc_impl(SoftCPU& cpu, T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -583,7 +583,7 @@ ALWAYS_INLINE static T op_and(SoftCPU& cpu, const T& dest, const T& src)
: "=a"(result)
: "a"(dest.value()), "c"(src.value()));
} else {
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
asm volatile(
@ -1152,7 +1152,7 @@ ALWAYS_INLINE void BTx_RM16_imm8(SoftCPU& cpu, const X86::Instruction& insn, Op
unsigned bit_index = insn.imm8() & (X86::TypeTrivia<u16>::mask);
// FIXME: Support higher bit indices
ASSERT(bit_index < 16);
VERIFY(bit_index < 16);
auto original = insn.modrm().read16(cpu, insn);
u16 bit_mask = 1 << bit_index;
@ -1169,7 +1169,7 @@ ALWAYS_INLINE void BTx_RM32_imm8(SoftCPU& cpu, const X86::Instruction& insn, Op
unsigned bit_index = insn.imm8() & (X86::TypeTrivia<u32>::mask);
// FIXME: Support higher bit indices
ASSERT(bit_index < 32);
VERIFY(bit_index < 32);
auto original = insn.modrm().read32(cpu, insn);
u32 bit_mask = 1 << bit_index;
@ -1551,7 +1551,7 @@ void SoftCPU::FLD_RM32(const X86::Instruction& insn)
void SoftCPU::FXCH(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
auto tmp = fpu_get(0);
fpu_set(0, fpu_get(insn.modrm().register_index()));
fpu_set(insn.modrm().register_index(), tmp);
@ -1559,7 +1559,7 @@ void SoftCPU::FXCH(const X86::Instruction& insn)
void SoftCPU::FST_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
float f32 = (float)fpu_get(0);
// FIXME: Respect shadow values
insn.modrm().write32(*this, insn, shadow_wrap_as_initialized(bit_cast<u32>(f32)));
@ -1645,7 +1645,7 @@ void SoftCPU::FCOS(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FIADD_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, fpu_get(0) + (long double)m32int);
@ -1655,7 +1655,7 @@ void SoftCPU::FCMOVB(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FIMUL_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, fpu_get(0) * (long double)m32int);
@ -1675,7 +1675,7 @@ void SoftCPU::FCMOVU(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FISUB_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, fpu_get(0) - (long double)m32int);
@ -1683,7 +1683,7 @@ void SoftCPU::FISUB_RM32(const X86::Instruction& insn)
void SoftCPU::FISUBR_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, (long double)m32int - fpu_get(0));
@ -1693,7 +1693,7 @@ void SoftCPU::FUCOMPP(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FIDIV_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
// FIXME: Raise IA on 0 / _=0, raise Z on finite / +-0
@ -1702,7 +1702,7 @@ void SoftCPU::FIDIV_RM32(const X86::Instruction& insn)
void SoftCPU::FIDIVR_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
// FIXME: Raise IA on 0 / _=0, raise Z on finite / +-0
@ -1711,7 +1711,7 @@ void SoftCPU::FIDIVR_RM32(const X86::Instruction& insn)
void SoftCPU::FILD_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m32int = (i32)insn.modrm().read32(*this, insn).value();
// FIXME: Respect shadow values
fpu_push((long double)m32int);
@ -1723,7 +1723,7 @@ void SoftCPU::FCMOVNE(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FIST_RM32(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto f = fpu_get(0);
// FIXME: Respect rounding mode in m_fpu_cw.
auto i32 = static_cast<int32_t>(f);
@ -1871,7 +1871,7 @@ void SoftCPU::FDIVR_RM64(const X86::Instruction& insn)
void SoftCPU::FLD_RM64(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto new_f64 = insn.modrm().read64(*this, insn);
// FIXME: Respect shadow values
fpu_push(bit_cast<double>(new_f64.value()));
@ -1905,7 +1905,7 @@ void SoftCPU::FNSTSW(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FIADD_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, fpu_get(0) + (long double)m16int);
@ -1913,14 +1913,14 @@ void SoftCPU::FIADD_RM16(const X86::Instruction& insn)
void SoftCPU::FADDP(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
fpu_set(insn.modrm().register_index(), fpu_get(insn.modrm().register_index()) + fpu_get(0));
fpu_pop();
}
void SoftCPU::FIMUL_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, fpu_get(0) * (long double)m16int);
@ -1928,7 +1928,7 @@ void SoftCPU::FIMUL_RM16(const X86::Instruction& insn)
void SoftCPU::FMULP(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
fpu_set(insn.modrm().register_index(), fpu_get(insn.modrm().register_index()) * fpu_get(0));
fpu_pop();
}
@ -1939,7 +1939,7 @@ void SoftCPU::FCOMPP(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FISUB_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, fpu_get(0) - (long double)m16int);
@ -1947,14 +1947,14 @@ void SoftCPU::FISUB_RM16(const X86::Instruction& insn)
void SoftCPU::FSUBRP(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
fpu_set(insn.modrm().register_index(), fpu_get(0) - fpu_get(insn.modrm().register_index()));
fpu_pop();
}
void SoftCPU::FISUBR_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
fpu_set(0, (long double)m16int - fpu_get(0));
@ -1962,14 +1962,14 @@ void SoftCPU::FISUBR_RM16(const X86::Instruction& insn)
void SoftCPU::FSUBP(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
fpu_set(insn.modrm().register_index(), fpu_get(insn.modrm().register_index()) - fpu_get(0));
fpu_pop();
}
void SoftCPU::FIDIV_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
// FIXME: Raise IA on 0 / _=0, raise Z on finite / +-0
@ -1978,7 +1978,7 @@ void SoftCPU::FIDIV_RM16(const X86::Instruction& insn)
void SoftCPU::FDIVRP(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
// FIXME: Raise IA on + infinity / +-infinitiy, +-0 / +-0, raise Z on finite / +-0
fpu_set(insn.modrm().register_index(), fpu_get(0) / fpu_get(insn.modrm().register_index()));
fpu_pop();
@ -1986,7 +1986,7 @@ void SoftCPU::FDIVRP(const X86::Instruction& insn)
void SoftCPU::FIDIVR_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
// FIXME: Raise IA on 0 / _=0, raise Z on finite / +-0
@ -1995,7 +1995,7 @@ void SoftCPU::FIDIVR_RM16(const X86::Instruction& insn)
void SoftCPU::FDIVP(const X86::Instruction& insn)
{
ASSERT(insn.modrm().is_register());
VERIFY(insn.modrm().is_register());
// FIXME: Raise IA on + infinity / +-infinitiy, +-0 / +-0, raise Z on finite / +-0
fpu_set(insn.modrm().register_index(), fpu_get(insn.modrm().register_index()) / fpu_get(0));
fpu_pop();
@ -2003,7 +2003,7 @@ void SoftCPU::FDIVP(const X86::Instruction& insn)
void SoftCPU::FILD_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m16int = (i16)insn.modrm().read16(*this, insn).value();
// FIXME: Respect shadow values
fpu_push((long double)m16int);
@ -2014,7 +2014,7 @@ void SoftCPU::FISTTP_RM16(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FIST_RM16(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto f = fpu_get(0);
// FIXME: Respect rounding mode in m_fpu_cw.
auto i16 = static_cast<int16_t>(f);
@ -2033,7 +2033,7 @@ void SoftCPU::FNSTSW_AX(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::FILD_RM64(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto m64int = (i64)insn.modrm().read64(*this, insn).value();
// FIXME: Respect shadow values
fpu_push((long double)m64int);
@ -2055,7 +2055,7 @@ void SoftCPU::FCOMIP(const X86::Instruction& insn)
void SoftCPU::FISTP_RM64(const X86::Instruction& insn)
{
ASSERT(!insn.modrm().is_register());
VERIFY(!insn.modrm().is_register());
auto f = fpu_pop();
// FIXME: Respect rounding mode in m_fpu_cw.
auto i64 = static_cast<int64_t>(f);
@ -2241,7 +2241,7 @@ void SoftCPU::INTO(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::INT_imm8(const X86::Instruction& insn)
{
ASSERT(insn.imm8() == 0x82);
VERIFY(insn.imm8() == 0x82);
// FIXME: virt_syscall should take ValueWithShadow and whine about uninitialized arguments
set_eax(shadow_wrap_as_initialized(m_emulator.virt_syscall(eax().value(), edx().value(), ecx().value(), ebx().value())));
}
@ -2745,7 +2745,7 @@ void SoftCPU::PUSH_imm32(const X86::Instruction& insn)
void SoftCPU::PUSH_imm8(const X86::Instruction& insn)
{
ASSERT(!insn.has_operand_size_override_prefix());
VERIFY(!insn.has_operand_size_override_prefix());
push32(shadow_wrap_as_initialized<u32>(sign_extended_to<i32>(insn.imm8())));
}
@ -2872,7 +2872,7 @@ void SoftCPU::RDTSC(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::RET(const X86::Instruction& insn)
{
ASSERT(!insn.has_operand_size_override_prefix());
VERIFY(!insn.has_operand_size_override_prefix());
auto ret_address = pop32();
warn_if_uninitialized(ret_address, "ret");
set_eip(ret_address.value());
@ -2883,7 +2883,7 @@ void SoftCPU::RETF_imm16(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::RET_imm16(const X86::Instruction& insn)
{
ASSERT(!insn.has_operand_size_override_prefix());
VERIFY(!insn.has_operand_size_override_prefix());
auto ret_address = pop32();
warn_if_uninitialized(ret_address, "ret imm16");
set_eip(ret_address.value());

10
Userland/DevTools/UserspaceEmulator/SoftCPU.h
View file

@ -118,7 +118,7 @@ public:
case X86::RegisterDH:
return { m_gpr[X86::RegisterEDX].high_u8, m_gpr_shadow[X86::RegisterEDX].high_u8 };
}
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
ValueWithShadow<u8> const_gpr8(X86::RegisterIndex8 reg) const
@ -141,7 +141,7 @@ public:
case X86::RegisterDH:
return { m_gpr[X86::RegisterEDX].high_u8, m_gpr_shadow[X86::RegisterEDX].high_u8 };
}
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
ValueWithShadow<u16> const_gpr16(X86::RegisterIndex16 reg) const
@ -431,7 +431,7 @@ public:
case 15:
return !((sf() ^ of()) | zf()); // NLE, G
default:
ASSERT_NOT_REACHED();
VERIFY_NOT_REACHED();
}
return 0;
}
@ -1140,12 +1140,12 @@ private:
}
long double fpu_get(int i)
{
ASSERT(i >= 0 && i <= m_fpu_top);
VERIFY(i >= 0 && i <= m_fpu_top);
return m_fpu[m_fpu_top - i];
}
void fpu_set(int i, long double n)
{
ASSERT(i >= 0 && i <= m_fpu_top);
VERIFY(i >= 0 && i <= m_fpu_top);
m_fpu[m_fpu_top - i] = n;
}

4
Userland/DevTools/UserspaceEmulator/SoftMMU.cpp
View file

@ -40,7 +40,7 @@ SoftMMU::SoftMMU(Emulator& emulator)
void SoftMMU::add_region(NonnullOwnPtr<Region> region)
{
ASSERT(!find_region({ 0x23, region->base() }));
VERIFY(!find_region({ 0x23, region->base() }));
size_t first_page_in_region = region->base() / PAGE_SIZE;
size_t last_page_in_region = (region->base() + region->size() - 1) / PAGE_SIZE;
@ -63,7 +63,7 @@ void SoftMMU::remove_region(Region& region)
void SoftMMU::set_tls_region(NonnullOwnPtr<Region> region)
{
ASSERT(!m_tls_region);
VERIFY(!m_tls_region);
m_tls_region = move(region);
}