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Everywhere: Rename ASSERT => VERIFY
(...and ASSERT_NOT_REACHED => VERIFY_NOT_REACHED) Since all of these checks are done in release builds as well, let's rename them to VERIFY to prevent confusion, as everyone is used to assertions being compiled out in release. We can introduce a new ASSERT macro that is specifically for debug checks, but I'm doing this wholesale conversion first since we've accumulated thousands of these already, and it's not immediately obvious which ones are suitable for ASSERT.
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b33a6a443e
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5d180d1f99
725 changed files with 3448 additions and 3448 deletions
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@ -195,7 +195,7 @@ static void build(InstructionDescriptor* table, u8 op, const char* mnemonic, Ins
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static void build_slash(InstructionDescriptor* table, u8 op, u8 slash, const char* mnemonic, InstructionFormat format, InstructionHandler handler, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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InstructionDescriptor& d = table[op];
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ASSERT(d.handler == nullptr);
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VERIFY(d.handler == nullptr);
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d.format = MultibyteWithSlash;
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d.has_rm = true;
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if (!d.slashes)
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@ -206,11 +206,11 @@ static void build_slash(InstructionDescriptor* table, u8 op, u8 slash, const cha
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static void build_slash_rm(InstructionDescriptor* table, u8 op, u8 slash, u8 rm, const char* mnemonic, InstructionFormat format, InstructionHandler handler)
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{
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ASSERT((rm & 0xc0) == 0xc0);
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ASSERT(((rm >> 3) & 7) == slash);
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VERIFY((rm & 0xc0) == 0xc0);
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VERIFY(((rm >> 3) & 7) == slash);
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InstructionDescriptor& d0 = table[op];
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ASSERT(d0.format == MultibyteWithSlash);
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VERIFY(d0.format == MultibyteWithSlash);
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InstructionDescriptor& d = d0.slashes[slash];
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if (!d.slashes) {
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@ -937,19 +937,19 @@ String MemoryOrRegisterReference::to_string_o32(const Instruction& insn) const
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String MemoryOrRegisterReference::to_string_fpu_reg() const
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{
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ASSERT(is_register());
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VERIFY(is_register());
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return register_name(reg_fpu());
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}
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String MemoryOrRegisterReference::to_string_fpu_mem(const Instruction& insn) const
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{
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ASSERT(!is_register());
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VERIFY(!is_register());
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return String::format("[%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_fpu_ax16() const
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{
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ASSERT(is_register());
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VERIFY(is_register());
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return register_name(reg16());
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}
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@ -976,7 +976,7 @@ String MemoryOrRegisterReference::to_string_fpu64(const Instruction& insn) const
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String MemoryOrRegisterReference::to_string_fpu80(const Instruction& insn) const
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{
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ASSERT(!is_register());
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VERIFY(!is_register());
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return String::format("tbyte ptr [%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_mm(const Instruction& insn) const
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@ -1824,7 +1824,7 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
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String Instruction::mnemonic() const
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{
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if (!m_descriptor) {
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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}
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return m_descriptor->mnemonic;
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}
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@ -641,7 +641,7 @@ ALWAYS_INLINE u32 MemoryOrRegisterReference::evaluate_sib(const CPU& cpu, Segmen
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base += cpu.ebp().value();
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break;
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default:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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break;
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}
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break;
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@ -689,7 +689,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::write32(CPU& cpu, const Instructio
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template<typename CPU, typename T>
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ALWAYS_INLINE void MemoryOrRegisterReference::write64(CPU& cpu, const Instruction& insn, T value)
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{
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ASSERT(!is_register());
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VERIFY(!is_register());
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auto address = resolve(cpu, insn);
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cpu.write_memory64(address, value);
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}
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@ -727,7 +727,7 @@ ALWAYS_INLINE typename CPU::ValueWithShadowType32 MemoryOrRegisterReference::rea
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template<typename CPU>
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ALWAYS_INLINE typename CPU::ValueWithShadowType64 MemoryOrRegisterReference::read64(CPU& cpu, const Instruction& insn)
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{
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ASSERT(!is_register());
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VERIFY(!is_register());
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auto address = resolve(cpu, insn);
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return cpu.read_memory64(address);
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}
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@ -864,7 +864,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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m_imm2 = stream.read32();
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break;
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default:
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ASSERT(imm2_bytes == 0);
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VERIFY(imm2_bytes == 0);
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break;
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}
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@ -879,7 +879,7 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
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m_imm1 = stream.read32();
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break;
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default:
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ASSERT(imm1_bytes == 0);
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VERIFY(imm1_bytes == 0);
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break;
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}
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@ -910,7 +910,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stre
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m_displacement32 = stream.read32();
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break;
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default:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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break;
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}
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} else {
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@ -925,7 +925,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode(InstructionStreamType& stre
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m_displacement16 = stream.read16();
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break;
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default:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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break;
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}
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}
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@ -939,7 +939,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode16(InstructionStreamType&)
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if ((m_rm & 0x07) == 6)
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m_displacement_bytes = 2;
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else
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ASSERT(m_displacement_bytes == 0);
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VERIFY(m_displacement_bytes == 0);
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break;
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case 0x40:
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m_displacement_bytes = 1;
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@ -987,7 +987,7 @@ ALWAYS_INLINE void MemoryOrRegisterReference::decode32(InstructionStreamType& st
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m_displacement_bytes = 4;
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break;
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default:
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ASSERT_NOT_REACHED();
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VERIFY_NOT_REACHED();
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break;
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}
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}
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