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Kernel/PCI: Move the PCI components as a subfolder to the Bus directory

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This commit is contained in:
Liav A 2021-06-25 09:46:17 +03:00 • committed by Andreas Kling
parent 26e9140ea1
commit 6568bb47cb
43 changed files with 60 additions and 60 deletions
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460
Kernel/Bus/PCI/Access.cpp Normal file
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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/Bus/PCI/Access.h>
#include <Kernel/Bus/PCI/IOAccess.h>
#include <Kernel/Debug.h>
#include <Kernel/IO.h>
#include <Kernel/Sections.h>
namespace Kernel {
namespace PCI {
static Access* s_access;
inline void write8(Address address, u32 field, u8 value) { Access::the().write8_field(address, field, value); }
inline void write16(Address address, u32 field, u16 value) { Access::the().write16_field(address, field, value); }
inline void write32(Address address, u32 field, u32 value) { Access::the().write32_field(address, field, value); }
inline u8 read8(Address address, u32 field) { return Access::the().read8_field(address, field); }
inline u16 read16(Address address, u32 field) { return Access::the().read16_field(address, field); }
inline u32 read32(Address address, u32 field) { return Access::the().read32_field(address, field); }
Access& Access::the()
{
if (s_access == nullptr) {
VERIFY_NOT_REACHED(); // We failed to initialize the PCI subsystem, so stop here!
}
return *s_access;
}
bool Access::is_initialized()
{
return (s_access != nullptr);
}
UNMAP_AFTER_INIT Access::Access()
: m_enumerated_buses(256, false)
{
s_access = this;
}
PhysicalID Access::get_physical_id(Address address) const
{
for (auto physical_id : m_physical_ids) {
if (physical_id.address().seg() == address.seg()
&& physical_id.address().bus() == address.bus()
&& physical_id.address().device() == address.device()
&& physical_id.address().function() == address.function()) {
return physical_id;
}
}
VERIFY_NOT_REACHED();
}
u8 Access::early_read8_field(Address address, u32 field)
{
dbgln_if(PCI_DEBUG, "PCI: Early reading 8-bit field {:#08x} for {}", field, address);
IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
return IO::in8(PCI_VALUE_PORT + (field & 3));
}
u16 Access::early_read16_field(Address address, u32 field)
{
dbgln_if(PCI_DEBUG, "PCI: Early reading 16-bit field {:#08x} for {}", field, address);
IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
return IO::in16(PCI_VALUE_PORT + (field & 2));
}
u32 Access::early_read32_field(Address address, u32 field)
{
dbgln_if(PCI_DEBUG, "PCI: Early reading 32-bit field {:#08x} for {}", field, address);
IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
return IO::in32(PCI_VALUE_PORT);
}
u16 Access::early_read_type(Address address)
{
dbgln_if(PCI_DEBUG, "PCI: Early reading type for {}", address);
return (early_read8_field(address, PCI_CLASS) << 8u) | early_read8_field(address, PCI_SUBCLASS);
}
UNMAP_AFTER_INIT void Access::enumerate_functions(int type, u8 bus, u8 device, u8 function, Function<void(Address, ID)>& callback, bool recursive)
{
dbgln_if(PCI_DEBUG, "PCI: Enumerating function type={}, bus={}, device={}, function={}", type, bus, device, function);
Address address(0, bus, device, function);
if (type == -1 || type == early_read_type(address))
callback(address, { early_read16_field(address, PCI_VENDOR_ID), early_read16_field(address, PCI_DEVICE_ID) });
if (early_read_type(address) == PCI_TYPE_BRIDGE && recursive && (!m_enumerated_buses.get(early_read8_field(address, PCI_SECONDARY_BUS)))) {
u8 secondary_bus = early_read8_field(address, PCI_SECONDARY_BUS);
dbgln_if(PCI_DEBUG, "PCI: Found secondary bus: {}", secondary_bus);
VERIFY(secondary_bus != bus);
m_enumerated_buses.set(secondary_bus, true);
enumerate_bus(type, secondary_bus, callback, recursive);
}
}
UNMAP_AFTER_INIT void Access::enumerate_device(int type, u8 bus, u8 device, Function<void(Address, ID)>& callback, bool recursive)
{
dbgln_if(PCI_DEBUG, "PCI: Enumerating device type={}, bus={}, device={}", type, bus, device);
Address address(0, bus, device, 0);
if (early_read16_field(address, PCI_VENDOR_ID) == PCI_NONE)
return;
enumerate_functions(type, bus, device, 0, callback, recursive);
if (!(early_read8_field(address, PCI_HEADER_TYPE) & 0x80))
return;
for (u8 function = 1; function < 8; ++function) {
Address address(0, bus, device, function);
if (early_read16_field(address, PCI_VENDOR_ID) != PCI_NONE)
enumerate_functions(type, bus, device, function, callback, recursive);
}
}
UNMAP_AFTER_INIT void Access::enumerate_bus(int type, u8 bus, Function<void(Address, ID)>& callback, bool recursive)
{
dbgln_if(PCI_DEBUG, "PCI: Enumerating bus type={}, bus={}", type, bus);
for (u8 device = 0; device < 32; ++device)
enumerate_device(type, bus, device, callback, recursive);
}
void Access::enumerate(Function<void(Address, ID)>& callback) const
{
for (auto& physical_id : m_physical_ids) {
callback(physical_id.address(), physical_id.id());
}
}
void enumerate(Function<void(Address, ID)> callback)
{
Access::the().enumerate(callback);
}
UNMAP_AFTER_INIT Optional<u8> get_capabilities_pointer(Address address)
{
dbgln_if(PCI_DEBUG, "PCI: Getting capabilities pointer for {}", address);
if (PCI::read16(address, PCI_STATUS) & (1 << 4)) {
dbgln_if(PCI_DEBUG, "PCI: Found capabilities pointer for {}", address);
return PCI::read8(address, PCI_CAPABILITIES_POINTER);
}
dbgln_if(PCI_DEBUG, "PCI: No capabilities pointer for {}", address);
return {};
}
PhysicalID get_physical_id(Address address)
{
return Access::the().get_physical_id(address);
}
UNMAP_AFTER_INIT Vector<Capability> get_capabilities(Address address)
{
dbgln_if(PCI_DEBUG, "PCI: Getting capabilities for {}", address);
auto capabilities_pointer = PCI::get_capabilities_pointer(address);
if (!capabilities_pointer.has_value()) {
dbgln_if(PCI_DEBUG, "PCI: No capabilities for {}", address);
return {};
}
Vector<Capability> capabilities;
auto capability_pointer = capabilities_pointer.value();
while (capability_pointer != 0) {
dbgln_if(PCI_DEBUG, "PCI: Reading in capability at {:#02x} for {}", capability_pointer, address);
u16 capability_header = PCI::read16(address, capability_pointer);
u8 capability_id = capability_header & 0xff;
capabilities.append({ address, capability_id, capability_pointer });
capability_pointer = capability_header >> 8;
}
return capabilities;
}
void raw_access(Address address, u32 field, size_t access_size, u32 value)
{
VERIFY(access_size != 0);
if (access_size == 1) {
write8(address, field, value);
return;
}
if (access_size == 2) {
write16(address, field, value);
return;
}
if (access_size == 4) {
write32(address, field, value);
return;
}
VERIFY_NOT_REACHED();
}
ID get_id(Address address)
{
return { read16(address, PCI_VENDOR_ID), read16(address, PCI_DEVICE_ID) };
}
void enable_io_space(Address address)
{
write16(address, PCI_COMMAND, read16(address, PCI_COMMAND) | (1 << 0));
}
void disable_io_space(Address address)
{
write16(address, PCI_COMMAND, read16(address, PCI_COMMAND) & ~(1 << 0));
}
void enable_memory_space(Address address)
{
write16(address, PCI_COMMAND, read16(address, PCI_COMMAND) | (1 << 1));
}
void disable_memory_space(Address address)
{
write16(address, PCI_COMMAND, read16(address, PCI_COMMAND) & ~(1 << 1));
}
bool is_io_space_enabled(Address address)
{
return (read16(address, PCI_COMMAND) & 1) != 0;
}
void enable_interrupt_line(Address address)
{
write16(address, PCI_COMMAND, read16(address, PCI_COMMAND) & ~(1 << 10));
}
void disable_interrupt_line(Address address)
{
write16(address, PCI_COMMAND, read16(address, PCI_COMMAND) | 1 << 10);
}
u8 get_interrupt_line(Address address)
{
return read8(address, PCI_INTERRUPT_LINE);
}
u32 get_BAR0(Address address)
{
return read32(address, PCI_BAR0);
}
u32 get_BAR1(Address address)
{
return read32(address, PCI_BAR1);
}
u32 get_BAR2(Address address)
{
return read32(address, PCI_BAR2);
}
u32 get_BAR3(Address address)
{
return read16(address, PCI_BAR3);
}
u32 get_BAR4(Address address)
{
return read32(address, PCI_BAR4);
}
u32 get_BAR5(Address address)
{
return read32(address, PCI_BAR5);
}
u32 get_BAR(Address address, u8 bar)
{
VERIFY(bar <= 5);
switch (bar) {
case 0:
return get_BAR0(address);
case 1:
return get_BAR1(address);
case 2:
return get_BAR2(address);
case 3:
return get_BAR3(address);
case 4:
return get_BAR4(address);
case 5:
return get_BAR5(address);
default:
VERIFY_NOT_REACHED();
}
}
u8 get_revision_id(Address address)
{
return read8(address, PCI_REVISION_ID);
}
u8 get_subclass(Address address)
{
return read8(address, PCI_SUBCLASS);
}
u8 get_class(Address address)
{
return read8(address, PCI_CLASS);
}
u8 get_programming_interface(Address address)
{
return read8(address, PCI_PROG_IF);
}
u16 get_subsystem_id(Address address)
{
return read16(address, PCI_SUBSYSTEM_ID);
}
u16 get_subsystem_vendor_id(Address address)
{
return read16(address, PCI_SUBSYSTEM_VENDOR_ID);
}
void enable_bus_mastering(Address address)
{
auto value = read16(address, PCI_COMMAND);
value |= (1 << 2);
value |= (1 << 0);
write16(address, PCI_COMMAND, value);
}
void disable_bus_mastering(Address address)
{
auto value = read16(address, PCI_COMMAND);
value &= ~(1 << 2);
value |= (1 << 0);
write16(address, PCI_COMMAND, value);
}
size_t get_BAR_space_size(Address address, u8 bar_number)
{
// See PCI Spec 2.3, Page 222
VERIFY(bar_number < 6);
u8 field = (PCI_BAR0 + (bar_number << 2));
u32 bar_reserved = read32(address, field);
write32(address, field, 0xFFFFFFFF);
u32 space_size = read32(address, field);
write32(address, field, bar_reserved);
space_size &= 0xfffffff0;
space_size = (~space_size) + 1;
return space_size;
}
u8 Capability::read8(u32 field) const
{
return PCI::read8(m_address, m_ptr + field);
}
u16 Capability::read16(u32 field) const
{
return PCI::read16(m_address, m_ptr + field);
}
u32 Capability::read32(u32 field) const
{
return PCI::read32(m_address, m_ptr + field);
}
void Capability::write8(u32 field, u8 value)
{
PCI::write8(m_address, m_ptr + field, value);
}
void Capability::write16(u32 field, u16 value)
{
PCI::write16(m_address, m_ptr + field, value);
}
void Capability::write32(u32 field, u32 value)
{
PCI::write32(m_address, m_ptr + field, value);
}
UNMAP_AFTER_INIT NonnullRefPtr<ExposedDeviceFolder> ExposedDeviceFolder::create(const SystemExposedFolder& parent_folder, Address address)
{
return adopt_ref(*new (nothrow) ExposedDeviceFolder(parent_folder, address));
}
UNMAP_AFTER_INIT ExposedDeviceFolder::ExposedDeviceFolder(const SystemExposedFolder& parent_folder, Address address)
: SystemExposedFolder(String::formatted("{:04x}:{:04x}:{:02x}.{}", address.seg(), address.bus(), address.device(), address.function()), parent_folder)
{
m_components.append(ExposedAttribute::create("vendor", *this, PCI_VENDOR_ID, 2));
m_components.append(ExposedAttribute::create("device_id", *this, PCI_DEVICE_ID, 2));
m_components.append(ExposedAttribute::create("class", *this, PCI_CLASS, 1));
m_components.append(ExposedAttribute::create("subclass", *this, PCI_SUBCLASS, 1));
m_components.append(ExposedAttribute::create("revision", *this, PCI_REVISION_ID, 1));
m_components.append(ExposedAttribute::create("progif", *this, PCI_PROG_IF, 1));
m_components.append(ExposedAttribute::create("subsystem_vendor", *this, PCI_SUBSYSTEM_VENDOR_ID, 2));
m_components.append(ExposedAttribute::create("subsystem_id", *this, PCI_SUBSYSTEM_ID, 2));
}
UNMAP_AFTER_INIT void BusExposedFolder::initialize()
{
auto pci_folder = adopt_ref(*new (nothrow) BusExposedFolder());
SystemRegistrar::the().register_new_component(pci_folder);
}
UNMAP_AFTER_INIT BusExposedFolder::BusExposedFolder()
: SystemExposedFolder("pci", SystemRegistrar::the().root_folder())
{
PCI::enumerate([&](const Address& address, ID) {
auto pci_device = PCI::ExposedDeviceFolder::create(*this, address);
m_components.append(pci_device);
});
}
NonnullRefPtr<ExposedAttribute> ExposedAttribute::create(String name, const ExposedDeviceFolder& device, size_t offset, size_t field_bytes_width)
{
return adopt_ref(*new (nothrow) ExposedAttribute(name, device, offset, field_bytes_width));
}
ExposedAttribute::ExposedAttribute(String name, const ExposedDeviceFolder& device, size_t offset, size_t field_bytes_width)
: SystemExposedComponent(name)
, m_device(device)
, m_offset(offset)
, m_field_bytes_width(field_bytes_width)
{
}
KResultOr<size_t> ExposedAttribute::read_bytes(off_t offset, size_t count, UserOrKernelBuffer& buffer, FileDescription*) const
{
auto blob = try_to_generate_buffer();
if (!blob)
return KResult(EFAULT);
if ((size_t)offset >= blob->size())
return KSuccess;
ssize_t nread = min(static_cast<off_t>(blob->size() - offset), static_cast<off_t>(count));
if (!buffer.write(blob->data() + offset, nread))
return KResult(EFAULT);
return nread;
}
size_t ExposedAttribute::size() const
{
auto buffer = try_to_generate_buffer();
if (!buffer)
return 0;
return buffer->size();
}
OwnPtr<KBuffer> ExposedAttribute::try_to_generate_buffer() const
{
String value;
switch (m_field_bytes_width) {
case 1:
value = String::formatted("0x{:x}", PCI::read8(m_device->address(), m_offset));
break;
case 2:
value = String::formatted("0x{:x}", PCI::read16(m_device->address(), m_offset));
break;
case 4:
value = String::formatted("0x{:x}", PCI::read32(m_device->address(), m_offset));
break;
default:
VERIFY_NOT_REACHED();
}
return KBuffer::try_create_with_bytes(value.substring_view(0).bytes());
}
}
}

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Kernel/Bus/PCI/Access.h Normal file
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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/Bitmap.h>
#include <AK/String.h>
#include <AK/Vector.h>
#include <Kernel/Bus/PCI/Definitions.h>
#include <Kernel/FileSystem/SysFS.h>
namespace Kernel::PCI {
class BusExposedFolder final : public SystemExposedFolder {
public:
static void initialize();
private:
BusExposedFolder();
};
class ExposedDeviceFolder final : public SystemExposedFolder {
public:
static NonnullRefPtr<ExposedDeviceFolder> create(const SystemExposedFolder&, Address);
const Address& address() const { return m_address; }
private:
ExposedDeviceFolder(const SystemExposedFolder&, Address);
Address m_address;
};
class ExposedAttribute : public SystemExposedComponent {
public:
static NonnullRefPtr<ExposedAttribute> create(String name, const ExposedDeviceFolder& device, size_t offset, size_t field_bytes_width);
virtual KResultOr<size_t> read_bytes(off_t, size_t, UserOrKernelBuffer&, FileDescription*) const override;
virtual ~ExposedAttribute() {};
virtual size_t size() const override;
protected:
virtual OwnPtr<KBuffer> try_to_generate_buffer() const;
ExposedAttribute(String name, const ExposedDeviceFolder& device, size_t offset, size_t field_bytes_width);
NonnullRefPtr<ExposedDeviceFolder> m_device;
size_t m_offset;
size_t m_field_bytes_width;
};
class Access {
public:
void enumerate(Function<void(Address, ID)>&) const;
void enumerate_bus(int type, u8 bus, Function<void(Address, ID)>&, bool recursive);
void enumerate_functions(int type, u8 bus, u8 device, u8 function, Function<void(Address, ID)>& callback, bool recursive);
void enumerate_device(int type, u8 bus, u8 device, Function<void(Address, ID)>& callback, bool recursive);
static Access& the();
static bool is_initialized();
virtual uint32_t segment_count() const = 0;
virtual uint8_t segment_start_bus(u32 segment) const = 0;
virtual uint8_t segment_end_bus(u32 segment) const = 0;
virtual const char* access_type() const = 0;
virtual void write8_field(Address address, u32 field, u8 value) = 0;
virtual void write16_field(Address address, u32 field, u16 value) = 0;
virtual void write32_field(Address address, u32 field, u32 value) = 0;
virtual u8 read8_field(Address address, u32 field) = 0;
virtual u16 read16_field(Address address, u32 field) = 0;
virtual u32 read32_field(Address address, u32 field) = 0;
PhysicalID get_physical_id(Address address) const;
protected:
virtual void enumerate_hardware(Function<void(Address, ID)>) = 0;
u8 early_read8_field(Address address, u32 field);
u16 early_read16_field(Address address, u32 field);
u32 early_read32_field(Address address, u32 field);
u16 early_read_type(Address address);
Access();
virtual ~Access() = default;
Vector<PhysicalID> m_physical_ids;
Bitmap m_enumerated_buses;
};
}

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Kernel/Bus/PCI/Definitions.h Normal file
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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/Function.h>
#include <AK/String.h>
#include <AK/Types.h>
#include <AK/Vector.h>
#include <Kernel/Debug.h>
namespace Kernel {
#define PCI_VENDOR_ID 0x00 // word
#define PCI_DEVICE_ID 0x02 // word
#define PCI_COMMAND 0x04 // word
#define PCI_STATUS 0x06 // word
#define PCI_REVISION_ID 0x08 // byte
#define PCI_PROG_IF 0x09 // byte
#define PCI_SUBCLASS 0x0a // byte
#define PCI_CLASS 0x0b // byte
#define PCI_CACHE_LINE_SIZE 0x0c // byte
#define PCI_LATENCY_TIMER 0x0d // byte
#define PCI_HEADER_TYPE 0x0e // byte
#define PCI_BIST 0x0f // byte
#define PCI_BAR0 0x10 // u32
#define PCI_BAR1 0x14 // u32
#define PCI_BAR2 0x18 // u32
#define PCI_BAR3 0x1C // u32
#define PCI_BAR4 0x20 // u32
#define PCI_BAR5 0x24 // u32
#define PCI_SUBSYSTEM_ID 0x2C // u16
#define PCI_SUBSYSTEM_VENDOR_ID 0x2E // u16
#define PCI_CAPABILITIES_POINTER 0x34 // u8
#define PCI_INTERRUPT_LINE 0x3C // byte
#define PCI_SECONDARY_BUS 0x19 // byte
#define PCI_HEADER_TYPE_DEVICE 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_TYPE_BRIDGE 0x0604
#define PCI_ADDRESS_PORT 0xCF8
#define PCI_VALUE_PORT 0xCFC
#define PCI_NONE 0xFFFF
#define PCI_MAX_DEVICES_PER_BUS 32
#define PCI_MAX_BUSES 256
#define PCI_MAX_FUNCTIONS_PER_DEVICE 8
#define PCI_CAPABILITY_NULL 0x0
#define PCI_CAPABILITY_MSI 0x5
#define PCI_CAPABILITY_VENDOR_SPECIFIC 0x9
#define PCI_CAPABILITY_MSIX 0x11
namespace PCI {
struct ID {
u16 vendor_id { 0 };
u16 device_id { 0 };
bool is_null() const { return !vendor_id && !device_id; }
bool operator==(const ID& other) const
{
return vendor_id == other.vendor_id && device_id == other.device_id;
}
bool operator!=(const ID& other) const
{
return vendor_id != other.vendor_id || device_id != other.device_id;
}
};
struct Address {
public:
Address() = default;
Address(u16 seg)
: m_seg(seg)
, m_bus(0)
, m_device(0)
, m_function(0)
{
}
Address(u16 seg, u8 bus, u8 device, u8 function)
: m_seg(seg)
, m_bus(bus)
, m_device(device)
, m_function(function)
{
}
Address(const Address& address)
: m_seg(address.seg())
, m_bus(address.bus())
, m_device(address.device())
, m_function(address.function())
{
}
bool is_null() const { return !m_bus && !m_device && !m_function; }
operator bool() const { return !is_null(); }
// Disable default implementations that would use surprising integer promotion.
bool operator<=(const Address&) const = delete;
bool operator>=(const Address&) const = delete;
bool operator<(const Address&) const = delete;
bool operator>(const Address&) const = delete;
bool operator==(const Address& other) const
{
if (this == &other)
return true;
return m_seg == other.m_seg && m_bus == other.m_bus && m_device == other.m_device && m_function == other.m_function;
}
bool operator!=(const Address& other) const
{
return !(*this == other);
}
u16 seg() const { return m_seg; }
u8 bus() const { return m_bus; }
u8 device() const { return m_device; }
u8 function() const { return m_function; }
u32 io_address_for_field(u8 field) const
{
return 0x80000000u | (m_bus << 16u) | (m_device << 11u) | (m_function << 8u) | (field & 0xfc);
}
protected:
u32 m_seg { 0 };
u8 m_bus { 0 };
u8 m_device { 0 };
u8 m_function { 0 };
};
struct ChangeableAddress : public Address {
ChangeableAddress()
: Address(0)
{
}
explicit ChangeableAddress(u16 seg)
: Address(seg)
{
}
ChangeableAddress(u16 seg, u8 bus, u8 device, u8 function)
: Address(seg, bus, device, function)
{
}
void set_seg(u16 seg) { m_seg = seg; }
void set_bus(u8 bus) { m_bus = bus; }
void set_device(u8 device) { m_device = device; }
void set_function(u8 function) { m_function = function; }
bool operator==(const Address& address)
{
if (m_seg == address.seg() && m_bus == address.bus() && m_device == address.device() && m_function == address.function())
return true;
else
return false;
}
const ChangeableAddress& operator=(const Address& address)
{
set_seg(address.seg());
set_bus(address.bus());
set_device(address.device());
set_function(address.function());
return *this;
}
};
class Capability {
public:
Capability(const Address& address, u8 id, u8 ptr)
: m_address(address)
, m_id(id)
, m_ptr(ptr)
{
}
u8 id() const { return m_id; }
u8 read8(u32) const;
u16 read16(u32) const;
u32 read32(u32) const;
void write8(u32, u8);
void write16(u32, u16);
void write32(u32, u32);
private:
Address m_address;
const u8 m_id;
const u8 m_ptr;
};
class PhysicalID {
public:
PhysicalID(Address address, ID id, Vector<Capability> capabilities)
: m_address(address)
, m_id(id)
, m_capabilities(capabilities)
{
if constexpr (PCI_DEBUG) {
for (auto capability : capabilities)
dbgln("{} has capability {}", address, capability.id());
}
}
Vector<Capability> capabilities() const { return m_capabilities; }
const ID& id() const { return m_id; }
const Address& address() const { return m_address; }
private:
Address m_address;
ID m_id;
Vector<Capability> m_capabilities;
};
ID get_id(PCI::Address);
bool is_io_space_enabled(Address);
void enumerate(Function<void(Address, ID)> callback);
void enable_interrupt_line(Address);
void disable_interrupt_line(Address);
u8 get_interrupt_line(Address);
void raw_access(Address, u32, size_t, u32);
u32 get_BAR0(Address);
u32 get_BAR1(Address);
u32 get_BAR2(Address);
u32 get_BAR3(Address);
u32 get_BAR4(Address);
u32 get_BAR5(Address);
u32 get_BAR(Address address, u8 bar);
u8 get_revision_id(Address);
u8 get_programming_interface(Address);
u8 get_subclass(Address);
u8 get_class(Address);
u16 get_subsystem_id(Address);
u16 get_subsystem_vendor_id(Address);
size_t get_BAR_space_size(Address, u8);
Optional<u8> get_capabilities_pointer(Address);
Vector<Capability> get_capabilities(Address);
void enable_bus_mastering(Address);
void disable_bus_mastering(Address);
void enable_io_space(Address);
void disable_io_space(Address);
void enable_memory_space(Address);
void disable_memory_space(Address);
PhysicalID get_physical_id(Address address);
class Access;
class MMIOAccess;
class WindowedMMIOAccess;
class IOAccess;
class MMIOSegment;
class DeviceController;
class Device;
}
}
template<>
struct AK::Formatter<Kernel::PCI::Address> : Formatter<FormatString> {
void format(FormatBuilder& builder, Kernel::PCI::Address value)
{
return Formatter<FormatString>::format(
builder,
"PCI [{:04x}:{:02x}:{:02x}:{:02x}]", value.seg(), value.bus(), value.device(), value.function());
}
};
template<>
struct AK::Formatter<Kernel::PCI::ID> : Formatter<FormatString> {
void format(FormatBuilder& builder, Kernel::PCI::ID value)
{
return Formatter<FormatString>::format(
builder,
"PCI::ID [{:04x}:{:04x}]", value.vendor_id, value.device_id);
}
};

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/Bus/PCI/Device.h>
namespace Kernel {
namespace PCI {
Device::Device(Address address)
: IRQHandler(get_interrupt_line(address))
, m_pci_address(address)
{
// FIXME: Register PCI device somewhere...
}
Device::Device(Address address, u8 interrupt_vector)
: IRQHandler(interrupt_vector)
, m_pci_address(address)
{
// FIXME: Register PCI device somewhere...
}
Device::~Device()
{
// FIXME: Unregister the device
}
}
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/Types.h>
#include <Kernel/Bus/PCI/Definitions.h>
#include <Kernel/Interrupts/IRQHandler.h>
namespace Kernel {
class PCI::Device : public IRQHandler {
public:
Address pci_address() const { return m_pci_address; };
protected:
Device(Address pci_address);
Device(Address pci_address, u8 interrupt_vector);
~Device();
private:
Address m_pci_address;
};
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/Bus/PCI/DeviceController.h>
namespace Kernel {
namespace PCI {
DeviceController::DeviceController(Address address)
: m_pci_address(address)
{
}
bool DeviceController::is_msi_capable() const
{
for (auto capability : PCI::get_physical_id(pci_address()).capabilities()) {
if (capability.id() == PCI_CAPABILITY_MSI)
return true;
}
return false;
}
bool DeviceController::is_msix_capable() const
{
for (auto capability : PCI::get_physical_id(pci_address()).capabilities()) {
if (capability.id() == PCI_CAPABILITY_MSIX)
return true;
}
return false;
}
void DeviceController::enable_pin_based_interrupts() const
{
PCI::enable_interrupt_line(pci_address());
}
void DeviceController::disable_pin_based_interrupts() const
{
PCI::disable_interrupt_line(pci_address());
}
void DeviceController::enable_message_signalled_interrupts()
{
TODO();
}
void DeviceController::disable_message_signalled_interrupts()
{
TODO();
}
void DeviceController::enable_extended_message_signalled_interrupts()
{
TODO();
}
void DeviceController::disable_extended_message_signalled_interrupts()
{
TODO();
}
}
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/Types.h>
#include <Kernel/Bus/PCI/Definitions.h>
namespace Kernel {
class PCI::DeviceController {
public:
Address pci_address() const { return m_pci_address; };
virtual ~DeviceController() = default;
void enable_pin_based_interrupts() const;
void disable_pin_based_interrupts() const;
bool is_msi_capable() const;
bool is_msix_capable() const;
void enable_message_signalled_interrupts();
void disable_message_signalled_interrupts();
void enable_extended_message_signalled_interrupts();
void disable_extended_message_signalled_interrupts();
protected:
explicit DeviceController(Address pci_address);
private:
Address m_pci_address;
};
}

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/*
* Copyright (c) 2021, Gunnar Beutner <gbeutner@serenityos.org>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
namespace Kernel {
enum class PCIVendorID {
VirtIO = 0x1af4,
Intel = 0x8086,
WCH = 0x1c00,
RedHat = 0x1b36,
Realtek = 0x10ec
};
enum class PCIDeviceID {
VirtIOConsole = 0x1003,
VirtIOEntropy = 0x1005,
VirtIOGPU = 0x1050,
};
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/Bus/PCI/IOAccess.h>
#include <Kernel/Debug.h>
#include <Kernel/IO.h>
#include <Kernel/Sections.h>
namespace Kernel {
namespace PCI {
UNMAP_AFTER_INIT void IOAccess::initialize()
{
if (!Access::is_initialized()) {
new IOAccess();
dbgln_if(PCI_DEBUG, "PCI: IO access initialised.");
}
}
UNMAP_AFTER_INIT IOAccess::IOAccess()
{
dmesgln("PCI: Using I/O instructions for PCI configuration space access");
enumerate_hardware([&](const Address& address, ID id) {
m_physical_ids.append({ address, id, get_capabilities(address) });
});
}
u8 IOAccess::read8_field(Address address, u32 field)
{
dbgln_if(PCI_DEBUG, "PCI: IO Reading 8-bit field {:#08x} for {}", field, address);
return Access::early_read8_field(address, field);
}
u16 IOAccess::read16_field(Address address, u32 field)
{
dbgln_if(PCI_DEBUG, "PCI: IO Reading 16-bit field {:#08x} for {}", field, address);
return Access::early_read16_field(address, field);
}
u32 IOAccess::read32_field(Address address, u32 field)
{
dbgln_if(PCI_DEBUG, "PCI: IO Reading 32-bit field {:#08x} for {}", field, address);
return Access::early_read32_field(address, field);
}
void IOAccess::write8_field(Address address, u32 field, u8 value)
{
dbgln_if(PCI_DEBUG, "PCI: IO Writing to 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
IO::out8(PCI_VALUE_PORT + (field & 3), value);
}
void IOAccess::write16_field(Address address, u32 field, u16 value)
{
dbgln_if(PCI_DEBUG, "PCI: IO Writing to 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
IO::out16(PCI_VALUE_PORT + (field & 2), value);
}
void IOAccess::write32_field(Address address, u32 field, u32 value)
{
dbgln_if(PCI_DEBUG, "PCI: IO Writing to 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
IO::out32(PCI_ADDRESS_PORT, address.io_address_for_field(field));
IO::out32(PCI_VALUE_PORT, value);
}
void IOAccess::enumerate_hardware(Function<void(Address, ID)> callback)
{
dbgln_if(PCI_DEBUG, "PCI: IO enumerating hardware");
// First scan bus 0. Find any device on that bus, and if it's a PCI-to-PCI
// bridge, recursively scan it too.
m_enumerated_buses.set(0, true);
enumerate_bus(-1, 0, callback, true);
// Handle Multiple PCI host bridges on slot 0, device 0.
// If we happen to miss some PCI buses because they are not reachable through
// recursive PCI-to-PCI bridges starting from bus 0, we might find them here.
if ((read8_field(Address(), PCI_HEADER_TYPE) & 0x80) != 0) {
for (int bus = 1; bus < 256; ++bus) {
if (read16_field(Address(0, 0, 0, bus), PCI_VENDOR_ID) == PCI_NONE)
continue;
if (read16_field(Address(0, 0, 0, bus), PCI_CLASS) != 0x6)
continue;
if (m_enumerated_buses.get(bus))
continue;
enumerate_bus(-1, bus, callback, false);
m_enumerated_buses.set(bus, true);
}
}
}
}
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <Kernel/Bus/PCI/Access.h>
namespace Kernel {
namespace PCI {
class IOAccess final : public PCI::Access {
public:
static void initialize();
protected:
IOAccess();
private:
virtual void enumerate_hardware(Function<void(Address, ID)>) override;
virtual const char* access_type() const override { return "IOAccess"; };
virtual uint32_t segment_count() const override { return 1; };
virtual void write8_field(Address address, u32, u8) override final;
virtual void write16_field(Address address, u32, u16) override final;
virtual void write32_field(Address address, u32, u32) override final;
virtual u8 read8_field(Address address, u32) override;
virtual u16 read16_field(Address address, u32) override;
virtual u32 read32_field(Address address, u32) override;
virtual uint8_t segment_start_bus(u32) const override { return 0x0; }
virtual uint8_t segment_end_bus(u32) const override { return 0xFF; }
};
}
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/ACPI/Parser.h>
#include <Kernel/Bus/PCI/IOAccess.h>
#include <Kernel/Bus/PCI/Initializer.h>
#include <Kernel/Bus/PCI/MMIOAccess.h>
#include <Kernel/Bus/PCI/WindowedMMIOAccess.h>
#include <Kernel/CommandLine.h>
#include <Kernel/IO.h>
#include <Kernel/Panic.h>
#include <Kernel/Sections.h>
namespace Kernel {
namespace PCI {
static bool test_pci_io();
UNMAP_AFTER_INIT static PCIAccessLevel detect_optimal_access_type(PCIAccessLevel boot_determined)
{
if (!ACPI::is_enabled() || ACPI::Parser::the()->find_table("MCFG").is_null())
return PCIAccessLevel::IOAddressing;
if (boot_determined != PCIAccessLevel::IOAddressing)
return boot_determined;
if (test_pci_io())
return PCIAccessLevel::IOAddressing;
PANIC("No PCI bus access method detected!");
}
UNMAP_AFTER_INIT void initialize()
{
auto boot_determined = kernel_command_line().pci_access_level();
switch (detect_optimal_access_type(boot_determined)) {
case PCIAccessLevel::MappingPerDevice:
WindowedMMIOAccess::initialize(ACPI::Parser::the()->find_table("MCFG"));
break;
case PCIAccessLevel::MappingPerBus:
MMIOAccess::initialize(ACPI::Parser::the()->find_table("MCFG"));
break;
case PCIAccessLevel::IOAddressing:
IOAccess::initialize();
break;
default:
VERIFY_NOT_REACHED();
}
PCI::BusExposedFolder::initialize();
PCI::enumerate([&](const Address& address, ID id) {
dmesgln("{} {}", address, id);
});
}
UNMAP_AFTER_INIT bool test_pci_io()
{
dmesgln("Testing PCI via manual probing...");
u32 tmp = 0x80000000;
IO::out32(PCI_ADDRESS_PORT, tmp);
tmp = IO::in32(PCI_ADDRESS_PORT);
if (tmp == 0x80000000) {
dmesgln("PCI IO supported");
return true;
}
dmesgln("PCI IO not supported");
return false;
}
}
}

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/*
* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
namespace Kernel {
namespace PCI {
void initialize();
}
}

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/*
* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <AK/Optional.h>
#include <AK/StringView.h>
#include <Kernel/Arch/x86/InterruptDisabler.h>
#include <Kernel/Bus/PCI/MMIOAccess.h>
#include <Kernel/Debug.h>
#include <Kernel/Sections.h>
#include <Kernel/VM/MemoryManager.h>
namespace Kernel {
namespace PCI {
#define MEMORY_RANGE_PER_BUS (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS)
u32 MMIOAccess::segment_count() const
{
return m_segments.size();
}
u8 MMIOAccess::segment_start_bus(u32 seg) const
{
auto segment = m_segments.get(seg);
VERIFY(segment.has_value());
return segment.value().get_start_bus();
}
u8 MMIOAccess::segment_end_bus(u32 seg) const
{
auto segment = m_segments.get(seg);
VERIFY(segment.has_value());
return segment.value().get_end_bus();
}
PhysicalAddress MMIOAccess::determine_memory_mapped_bus_region(u32 segment, u8 bus) const
{
VERIFY(bus >= segment_start_bus(segment) && bus <= segment_end_bus(segment));
auto seg = m_segments.get(segment);
VERIFY(seg.has_value());
return seg.value().get_paddr().offset(MEMORY_RANGE_PER_BUS * (bus - seg.value().get_start_bus()));
}
UNMAP_AFTER_INIT void MMIOAccess::initialize(PhysicalAddress mcfg)
{
if (!Access::is_initialized()) {
new MMIOAccess(mcfg);
dbgln_if(PCI_DEBUG, "PCI: MMIO access initialised.");
}
}
UNMAP_AFTER_INIT MMIOAccess::MMIOAccess(PhysicalAddress p_mcfg)
: m_mcfg(p_mcfg)
{
dmesgln("PCI: Using MMIO for PCI configuration space access");
auto checkup_region = MM.allocate_kernel_region(p_mcfg.page_base(), (PAGE_SIZE * 2), "PCI MCFG Checkup", Region::Access::Read | Region::Access::Write);
dbgln_if(PCI_DEBUG, "PCI: Checking MCFG Table length to choose the correct mapping size");
auto* sdt = (ACPI::Structures::SDTHeader*)checkup_region->vaddr().offset(p_mcfg.offset_in_page()).as_ptr();
u32 length = sdt->length;
u8 revision = sdt->revision;
dbgln("PCI: MCFG, length: {}, revision: {}", length, revision);
checkup_region->unmap();
auto mcfg_region = MM.allocate_kernel_region(p_mcfg.page_base(), page_round_up(length) + PAGE_SIZE, "PCI Parsing MCFG", Region::Access::Read | Region::Access::Write);
auto& mcfg = *(ACPI::Structures::MCFG*)mcfg_region->vaddr().offset(p_mcfg.offset_in_page()).as_ptr();
dbgln_if(PCI_DEBUG, "PCI: Checking MCFG @ {}, {}", VirtualAddress(&mcfg), PhysicalAddress(p_mcfg.get()));
for (u32 index = 0; index < ((mcfg.header.length - sizeof(ACPI::Structures::MCFG)) / sizeof(ACPI::Structures::PCI_MMIO_Descriptor)); index++) {
u8 start_bus = mcfg.descriptors[index].start_pci_bus;
u8 end_bus = mcfg.descriptors[index].end_pci_bus;
u32 lower_addr = mcfg.descriptors[index].base_addr;
m_segments.set(index, { PhysicalAddress(lower_addr), start_bus, end_bus });
dmesgln("PCI: New PCI segment @ {}, PCI buses ({}-{})", PhysicalAddress { lower_addr }, start_bus, end_bus);
}
mcfg_region->unmap();
dmesgln("PCI: MMIO segments: {}", m_segments.size());
InterruptDisabler disabler;
VERIFY(m_segments.contains(0));
// Note: we need to map this region before enumerating the hardware and adding
// PCI::PhysicalID objects to the vector, because get_capabilities calls
// PCI::read16 which will need this region to be mapped.
u8 start_bus = m_segments.get(0).value().get_start_bus();
m_mapped_region = MM.allocate_kernel_region(determine_memory_mapped_bus_region(0, start_bus), MEMORY_RANGE_PER_BUS, "PCI ECAM", Region::Access::Read | Region::Access::Write);
m_mapped_bus = start_bus;
dbgln_if(PCI_DEBUG, "PCI: First PCI ECAM Mapped region for starting bus {} @ {} {}", start_bus, m_mapped_region->vaddr(), m_mapped_region->physical_page(0)->paddr());
enumerate_hardware([&](const Address& address, ID id) {
m_physical_ids.append({ address, id, get_capabilities(address) });
});
}
void MMIOAccess::map_bus_region(u32 segment, u8 bus)
{
VERIFY(m_access_lock.is_locked());
if (m_mapped_bus == bus)
return;
m_mapped_region = MM.allocate_kernel_region(determine_memory_mapped_bus_region(segment, bus), MEMORY_RANGE_PER_BUS, "PCI ECAM", Region::Access::Read | Region::Access::Write);
m_mapped_bus = bus;
dbgln_if(PCI_DEBUG, "PCI: New PCI ECAM Mapped region for bus {} @ {} {}", bus, m_mapped_region->vaddr(), m_mapped_region->physical_page(0)->paddr());
}
VirtualAddress MMIOAccess::get_device_configuration_space(Address address)
{
VERIFY(m_access_lock.is_locked());
dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
map_bus_region(address.seg(), address.bus());
return m_mapped_region->vaddr().offset(PCI_MMIO_CONFIG_SPACE_SIZE * address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * address.device());
}
u8 MMIOAccess::read8_field(Address address, u32 field)
{
ScopedSpinLock lock(m_access_lock);
VERIFY(field <= 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 8-bit field {:#08x} for {}", field, address);
return *((volatile u8*)(get_device_configuration_space(address).get() + (field & 0xfff)));
}
u16 MMIOAccess::read16_field(Address address, u32 field)
{
ScopedSpinLock lock(m_access_lock);
VERIFY(field < 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 16-bit field {:#08x} for {}", field, address);
u16 data = 0;
read_possibly_unaligned_data<u16>(get_device_configuration_space(address).offset(field & 0xfff).as_ptr(), data);
return data;
}
u32 MMIOAccess::read32_field(Address address, u32 field)
{
ScopedSpinLock lock(m_access_lock);
VERIFY(field <= 0xffc);
dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 32-bit field {:#08x} for {}", field, address);
u32 data = 0;
read_possibly_unaligned_data<u32>(get_device_configuration_space(address).offset(field & 0xfff).as_ptr(), data);
return data;
}
void MMIOAccess::write8_field(Address address, u32 field, u8 value)
{
ScopedSpinLock lock(m_access_lock);
VERIFY(field <= 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
*((volatile u8*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
}
void MMIOAccess::write16_field(Address address, u32 field, u16 value)
{
ScopedSpinLock lock(m_access_lock);
VERIFY(field < 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
write_possibly_unaligned_data<u16>(get_device_configuration_space(address).offset(field & 0xfff).as_ptr(), value);
}
void MMIOAccess::write32_field(Address address, u32 field, u32 value)
{
ScopedSpinLock lock(m_access_lock);
VERIFY(field <= 0xffc);
dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
write_possibly_unaligned_data<u32>(get_device_configuration_space(address).offset(field & 0xfff).as_ptr(), value);
}
void MMIOAccess::enumerate_hardware(Function<void(Address, ID)> callback)
{
for (u16 seg = 0; seg < m_segments.size(); seg++) {
dbgln_if(PCI_DEBUG, "PCI: Enumerating Memory mapped IO segment {}", seg);
// Single PCI host controller.
if ((early_read8_field(Address(seg), PCI_HEADER_TYPE) & 0x80) == 0) {
enumerate_bus(-1, 0, callback, true);
return;
}
// Multiple PCI host controllers.
for (u8 function = 0; function < 8; ++function) {
if (early_read16_field(Address(seg, 0, 0, function), PCI_VENDOR_ID) == PCI_NONE)
break;
enumerate_bus(-1, function, callback, false);
}
}
}
MMIOAccess::MMIOSegment::MMIOSegment(PhysicalAddress segment_base_addr, u8 start_bus, u8 end_bus)
: m_base_addr(segment_base_addr)
, m_start_bus(start_bus)
, m_end_bus(end_bus)
{
}
u8 MMIOAccess::MMIOSegment::get_start_bus() const
{
return m_start_bus;
}
u8 MMIOAccess::MMIOSegment::get_end_bus() const
{
return m_end_bus;
}
size_t MMIOAccess::MMIOSegment::get_size() const
{
return (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS * (get_end_bus() - get_start_bus()));
}
PhysicalAddress MMIOAccess::MMIOSegment::get_paddr() const
{
return m_base_addr;
}
}
}

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/*
* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/HashMap.h>
#include <AK/NonnullOwnPtrVector.h>
#include <AK/OwnPtr.h>
#include <AK/Types.h>
#include <Kernel/ACPI/Definitions.h>
#include <Kernel/Bus/PCI/Access.h>
#include <Kernel/SpinLock.h>
#include <Kernel/VM/AnonymousVMObject.h>
#include <Kernel/VM/PhysicalRegion.h>
#include <Kernel/VM/Region.h>
#include <Kernel/VM/VMObject.h>
namespace Kernel {
namespace PCI {
#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
class MMIOAccess : public Access {
public:
class MMIOSegment {
public:
MMIOSegment(PhysicalAddress, u8, u8);
u8 get_start_bus() const;
u8 get_end_bus() const;
size_t get_size() const;
PhysicalAddress get_paddr() const;
private:
PhysicalAddress m_base_addr;
u8 m_start_bus;
u8 m_end_bus;
};
static void initialize(PhysicalAddress mcfg);
private:
PhysicalAddress determine_memory_mapped_bus_region(u32 segment, u8 bus) const;
void map_bus_region(u32, u8);
VirtualAddress get_device_configuration_space(Address address);
SpinLock<u8> m_access_lock;
u8 m_mapped_bus { 0 };
OwnPtr<Region> m_mapped_region;
protected:
explicit MMIOAccess(PhysicalAddress mcfg);
virtual const char* access_type() const override { return "MMIOAccess"; };
virtual u32 segment_count() const override;
virtual void enumerate_hardware(Function<void(Address, ID)>) override;
virtual void write8_field(Address address, u32, u8) override;
virtual void write16_field(Address address, u32, u16) override;
virtual void write32_field(Address address, u32, u32) override;
virtual u8 read8_field(Address address, u32) override;
virtual u16 read16_field(Address address, u32) override;
virtual u32 read32_field(Address address, u32) override;
virtual u8 segment_start_bus(u32) const override;
virtual u8 segment_end_bus(u32) const override;
PhysicalAddress m_mcfg;
HashMap<u16, MMIOSegment> m_segments;
};
}
}

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/*
* Copyright (c) 2020-2021, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <AK/Optional.h>
#include <AK/StringView.h>
#include <Kernel/Arch/x86/InterruptDisabler.h>
#include <Kernel/Bus/PCI/WindowedMMIOAccess.h>
#include <Kernel/Debug.h>
#include <Kernel/Sections.h>
#include <Kernel/VM/MemoryManager.h>
namespace Kernel {
namespace PCI {
UNMAP_AFTER_INIT DeviceConfigurationSpaceMapping::DeviceConfigurationSpaceMapping(Address device_address, const MMIOAccess::MMIOSegment& mmio_segment)
: m_device_address(device_address)
, m_mapped_region(MM.allocate_kernel_region(page_round_up(PCI_MMIO_CONFIG_SPACE_SIZE), "PCI MMIO Device Access", Region::Access::Read | Region::Access::Write).release_nonnull())
{
PhysicalAddress segment_lower_addr = mmio_segment.get_paddr();
PhysicalAddress device_physical_mmio_space = segment_lower_addr.offset(
PCI_MMIO_CONFIG_SPACE_SIZE * m_device_address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * m_device_address.device() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS) * (m_device_address.bus() - mmio_segment.get_start_bus()));
m_mapped_region->physical_page_slot(0) = PhysicalPage::create(device_physical_mmio_space, false, false);
m_mapped_region->remap();
}
UNMAP_AFTER_INIT void WindowedMMIOAccess::initialize(PhysicalAddress mcfg)
{
if (!Access::is_initialized()) {
new WindowedMMIOAccess(mcfg);
dbgln_if(PCI_DEBUG, "PCI: MMIO access initialised.");
}
}
UNMAP_AFTER_INIT WindowedMMIOAccess::WindowedMMIOAccess(PhysicalAddress p_mcfg)
: MMIOAccess(p_mcfg)
{
dmesgln("PCI: Using MMIO (mapping per device) for PCI configuration space access");
InterruptDisabler disabler;
enumerate_hardware([&](const Address& address, ID) {
m_mapped_device_regions.append(make<DeviceConfigurationSpaceMapping>(address, m_segments.get(address.seg()).value()));
});
}
Optional<VirtualAddress> WindowedMMIOAccess::get_device_configuration_space(Address address)
{
dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
for (auto& mapping : m_mapped_device_regions) {
auto checked_address = mapping.address();
dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Check if {} was requested", checked_address);
if (address.seg() == checked_address.seg()
&& address.bus() == checked_address.bus()
&& address.device() == checked_address.device()
&& address.function() == checked_address.function()) {
dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Found {}", checked_address);
return mapping.vaddr();
}
}
dbgln_if(PCI_DEBUG, "PCI: No device configuration space found for {}", address);
return {};
}
u8 WindowedMMIOAccess::read8_field(Address address, u32 field)
{
InterruptDisabler disabler;
VERIFY(field <= 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 8-bit field {:#08x} for {}", field, address);
return *((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
}
u16 WindowedMMIOAccess::read16_field(Address address, u32 field)
{
InterruptDisabler disabler;
VERIFY(field < 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 16-bit field {:#08x} for {}", field, address);
u16 data = 0;
read_possibly_unaligned_data<u16>(get_device_configuration_space(address).value().offset(field & 0xfff).as_ptr(), data);
return data;
}
u32 WindowedMMIOAccess::read32_field(Address address, u32 field)
{
InterruptDisabler disabler;
VERIFY(field <= 0xffc);
dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 32-bit field {:#08x} for {}", field, address);
u32 data = 0;
read_possibly_unaligned_data<u32>(get_device_configuration_space(address).value().offset(field & 0xfff).as_ptr(), data);
return data;
}
void WindowedMMIOAccess::write8_field(Address address, u32 field, u8 value)
{
InterruptDisabler disabler;
VERIFY(field <= 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
*((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
}
void WindowedMMIOAccess::write16_field(Address address, u32 field, u16 value)
{
InterruptDisabler disabler;
VERIFY(field < 0xfff);
dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
write_possibly_unaligned_data<u16>(get_device_configuration_space(address).value().offset(field & 0xfff).as_ptr(), value);
}
void WindowedMMIOAccess::write32_field(Address address, u32 field, u32 value)
{
InterruptDisabler disabler;
VERIFY(field <= 0xffc);
dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
write_possibly_unaligned_data<u32>(get_device_configuration_space(address).value().offset(field & 0xfff).as_ptr(), value);
}
}
}

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/*
* Copyright (c) 2020-2021, Liav A. <liavalb@hotmail.co.il>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#pragma once
#include <AK/HashMap.h>
#include <AK/NonnullOwnPtrVector.h>
#include <AK/OwnPtr.h>
#include <AK/Types.h>
#include <Kernel/ACPI/Definitions.h>
#include <Kernel/Bus/PCI/Access.h>
#include <Kernel/Bus/PCI/MMIOAccess.h>
#include <Kernel/VM/AnonymousVMObject.h>
#include <Kernel/VM/PhysicalRegion.h>
#include <Kernel/VM/Region.h>
#include <Kernel/VM/VMObject.h>
namespace Kernel {
namespace PCI {
class DeviceConfigurationSpaceMapping {
public:
DeviceConfigurationSpaceMapping(Address, const MMIOAccess::MMIOSegment&);
VirtualAddress vaddr() const { return m_mapped_region->vaddr(); };
PhysicalAddress paddr() const { return m_mapped_region->physical_page(0)->paddr(); }
const Address& address() const { return m_device_address; };
private:
Address m_device_address;
NonnullOwnPtr<Region> m_mapped_region;
};
class WindowedMMIOAccess final : public MMIOAccess {
public:
static void initialize(PhysicalAddress mcfg);
private:
explicit WindowedMMIOAccess(PhysicalAddress mcfg);
virtual const char* access_type() const override { return "WindowedMMIOAccess"; };
virtual void write8_field(Address address, u32, u8) override;
virtual void write16_field(Address address, u32, u16) override;
virtual void write32_field(Address address, u32, u32) override;
virtual u8 read8_field(Address address, u32) override;
virtual u16 read16_field(Address address, u32) override;
virtual u32 read32_field(Address address, u32) override;
Optional<VirtualAddress> get_device_configuration_space(Address address);
NonnullOwnPtrVector<DeviceConfigurationSpaceMapping> m_mapped_device_regions;
};
}
}