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Kernel: Add and use accessors to read from Aarch64 CPU ID registers

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Following registers accessors are updated and put in use:
* ID_AA64ISAR0_EL1, Instruction Set Attribute Register 0

Accessors for following registers are added and put in use:
* ID_AA64ISAR1_EL1, Instruction Set Attribute Register 1
* ID_AA64ISAR2_EL1, Instruction Set Attribute Register 2
* ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1
* ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2
* ID_AA64MMFR3_EL1, AArch64 Memory Model Feature Register 3
* ID_AA64MMFR4_EL1, AArch64 Memory Model Feature Register 4
* ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0
* ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1
* ID_AA64PFR2_EL1, AArch64 Processor Feature Register 2
* ID_AA64ZFR0_EL1, AArch64 SVE Feature ID register 0
* ID_AA64SMFR0_EL1, AArch64 SME Feature ID register 0
* ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0
* ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1

Additionally, there are few CPU features detected with
* TCR_EL1, Translation Control Register

but detection mechanism using it (for LPA/LPA2) is probably wrong as
this is control register, not a id register, and needs further work.

Finally, following registers are provided. Former one is already used,
while latter is given for future use:
* MIDR_EL1, Main ID Register
* AIDR_EL1, Auxiliary ID Register
This commit is contained in:
konrad 2023-01-02 21:07:02 +01:00 • committed by Jelle Raaijmakers
parent 6979cf230e
commit 66c65f6e2c
3 changed files with 861 additions and 7 deletions
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2
Kernel/Arch/aarch64/CPUID.h
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@ -270,7 +270,7 @@ AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
TRBE = CPUFeature(1u) << 239u, // Trace Buffer Extension
SME = CPUFeature(1u) << 240u, // Scalable Matrix Extension
__End = CPUFeature(1u) << 255u);
__End = CPUFeature(1u) << 255u); // XXX — SENTINEL VALUE — XXX
CPUFeature::Type detect_cpu_features();
StringView cpu_feature_to_name(CPUFeature::Type const&);