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Kernel/aarch64: Flush entire TLB cache when changing TTBR0_EL1

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Setting the page table base register (ttbr0_el1) is not enough, and will
not flush the TLB caches, in contrary with x86_64 where setting the CR3
register will actually flush the caches. This commit adds the necessary
code to properly flush the TLB caches when context switching. This
commit also changes Processor::flush_tlb_local to use the vmalle1
variant, as previously we would be flushing the tlb's of all the cores
in the inner-shareable domain.
This commit is contained in:
Timon Kruiper 2023-02-21 21:21:03 +01:00 • committed by Idan Horowitz
parent 188a52db01
commit 6a8581855d
3 changed files with 16 additions and 2 deletions
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2
Kernel/Arch/aarch64/PageDirectory.cpp
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@ -49,12 +49,14 @@ LockRefPtr<PageDirectory> PageDirectory::find_current()
void activate_kernel_page_directory(PageDirectory const& page_directory)
{
Aarch64::Asm::set_ttbr0_el1(page_directory.ttbr0());
Processor::flush_entire_tlb_local();
}
void activate_page_directory(PageDirectory const& page_directory, Thread* current_thread)
{
current_thread->regs().ttbr0_el1 = page_directory.ttbr0();
Aarch64::Asm::set_ttbr0_el1(page_directory.ttbr0());
Processor::flush_entire_tlb_local();
}
UNMAP_AFTER_INIT NonnullLockRefPtr<PageDirectory> PageDirectory::must_create_kernel_page_directory()