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https://github.com/RGBCube/serenity
synced 2025-05-31 22:48:11 +00:00
UserspaceEmulator: Delegate rounding to the actual hardware
This also makes us a bit more accurate, due to better rounding of intermediate results. This also gives us the flush-to-zero and denormals-are-zero SSE settings for free! (Assuming UE is build with SSE)
This commit is contained in:
Hendiadyoin1
Linus Groh
parent
56a31ab376
commit
6c41267dcf
5 changed files with 91 additions and 126 deletions
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@ -123,32 +123,32 @@ ALWAYS_INLINE void SoftFPU::fpu_set_exception(FPU_Exception ex)
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break;
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case FPU_Exception::InvalidOperation:
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m_fpu_error_invalid = 1;
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if (!m_fpu_mask_invalid)
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if (!m_fpu_cw.mask_invalid)
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break;
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return;
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case FPU_Exception::DenormalizedOperand:
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m_fpu_error_denorm = 1;
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if (!m_fpu_mask_denorm)
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if (!m_fpu_cw.mask_denorm)
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break;
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return;
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case FPU_Exception::ZeroDivide:
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m_fpu_error_zero_div = 1;
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if (!m_fpu_mask_zero_div)
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if (!m_fpu_cw.mask_zero_div)
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break;
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return;
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case FPU_Exception::Overflow:
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m_fpu_error_overflow = 1;
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if (!m_fpu_mask_overflow)
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if (!m_fpu_cw.mask_overflow)
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break;
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return;
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case FPU_Exception::Underflow:
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m_fpu_error_underflow = 1;
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if (!m_fpu_mask_underflow)
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if (!m_fpu_cw.mask_underflow)
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break;
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return;
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case FPU_Exception::Precision:
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m_fpu_error_precision = 1;
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if (!m_fpu_mask_precision)
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if (!m_fpu_cw.mask_precision)
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break;
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return;
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}
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@ -168,27 +168,9 @@ ALWAYS_INLINE void SoftFPU::fpu_set_exception(FPU_Exception ex)
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}
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template<Arithmetic T>
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ALWAYS_INLINE T SoftFPU::fpu_round(long double value) const
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ALWAYS_INLINE T SoftFPU::round_checked(long double value)
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{
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// FIXME: may need to set indefinite values manually
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switch (fpu_get_round_mode()) {
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case RoundingMode::NEAREST:
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return static_cast<T>(roundl(value));
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case RoundingMode::DOWN:
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return static_cast<T>(floorl(value));
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case RoundingMode::UP:
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return static_cast<T>(ceill(value));
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case RoundingMode::TRUNC:
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return static_cast<T>(truncl(value));
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default:
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VERIFY_NOT_REACHED();
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}
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}
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template<Arithmetic T>
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ALWAYS_INLINE T SoftFPU::fpu_round_checked(long double value)
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{
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T result = fpu_round<T>(value);
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T result = static_cast<T>(rintl(value));
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if (result != value)
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fpu_set_exception(FPU_Exception::Precision);
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if (result > value)
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@ -199,15 +181,9 @@ ALWAYS_INLINE T SoftFPU::fpu_round_checked(long double value)
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}
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template<FloatingPoint T>
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ALWAYS_INLINE T SoftFPU::fpu_convert(long double value) const
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ALWAYS_INLINE T SoftFPU::convert_checked(long double value)
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{
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// FIXME: actually round the right way
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return static_cast<T>(value);
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}
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template<FloatingPoint T>
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ALWAYS_INLINE T SoftFPU::fpu_convert_checked(long double value)
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{
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T result = fpu_convert<T>(value);
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T result = static_cast<T>(value);
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if (auto rnd = value - result) {
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if (rnd > 0)
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set_c1(1);
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@ -254,7 +230,7 @@ void SoftFPU::FLD_RM80(const X86::Instruction& insn)
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void SoftFPU::FST_RM32(const X86::Instruction& insn)
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{
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VERIFY(!insn.modrm().is_register());
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float f32 = fpu_convert_checked<float>(fpu_get(0));
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float f32 = convert_checked<float>(fpu_get(0));
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if (fpu_is_set(0))
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insn.modrm().write32(m_cpu, insn, shadow_wrap_as_initialized(bit_cast<u32>(f32)));
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@ -266,7 +242,7 @@ void SoftFPU::FST_RM64(const X86::Instruction& insn)
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if (insn.modrm().is_register()) {
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fpu_set(insn.modrm().register_index(), fpu_get(0));
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} else {
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double f64 = fpu_convert_checked<double>(fpu_get(0));
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double f64 = convert_checked<double>(fpu_get(0));
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if (fpu_is_set(0))
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insn.modrm().write64(m_cpu, insn, shadow_wrap_as_initialized(bit_cast<u64>(f64)));
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else
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@ -335,7 +311,7 @@ void SoftFPU::FIST_RM16(const X86::Instruction& insn)
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VERIFY(!insn.modrm().is_register());
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auto f = fpu_get(0);
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set_c1(0);
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auto int16 = fpu_round_checked<i16>(f);
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auto int16 = round_checked<i16>(f);
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// FIXME: Respect shadow values
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insn.modrm().write16(m_cpu, insn, shadow_wrap_as_initialized(bit_cast<u16>(int16)));
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@ -345,7 +321,7 @@ void SoftFPU::FIST_RM32(const X86::Instruction& insn)
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VERIFY(!insn.modrm().is_register());
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auto f = fpu_get(0);
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set_c1(0);
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auto int32 = fpu_round_checked<i32>(f);
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auto int32 = round_checked<i32>(f);
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// FIXME: Respect shadow values
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insn.modrm().write32(m_cpu, insn, shadow_wrap_as_initialized(bit_cast<u32>(int32)));
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}
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@ -365,7 +341,7 @@ void SoftFPU::FISTP_RM64(const X86::Instruction& insn)
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VERIFY(!insn.modrm().is_register());
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auto f = fpu_pop();
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set_c1(0);
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auto i64 = fpu_round_checked<int64_t>(f);
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auto i64 = round_checked<int64_t>(f);
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// FIXME: Respect shadow values
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insn.modrm().write64(m_cpu, insn, shadow_wrap_as_initialized(bit_cast<u64>(i64)));
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}
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@ -787,7 +763,7 @@ void SoftFPU::FCHS(const X86::Instruction&)
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void SoftFPU::FRNDINT(const X86::Instruction&)
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{
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// FIXME: Raise #IA #D
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auto res = fpu_round_checked<long double>(fpu_get(0));
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auto res = round_checked<long double>(fpu_get(0));
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fpu_set(0, res);
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}
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@ -818,7 +794,7 @@ void SoftFPU::FCOMPP(const X86::Instruction&)
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{
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if (fpu_isnan(0) || fpu_isnan(1)) {
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fpu_set_exception(FPU_Exception::InvalidOperation);
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if (m_fpu_mask_invalid)
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if (m_fpu_cw.mask_invalid)
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fpu_set_unordered();
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} else {
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set_c2(0);
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@ -1146,7 +1122,7 @@ void SoftFPU::FFREEP(const X86::Instruction& insn)
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void SoftFPU::FNINIT(const X86::Instruction&)
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{
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m_fpu_cw = 0x037F;
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m_fpu_cw.cw = 0x037F;
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m_fpu_sw = 0;
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m_fpu_tw = 0xFFFF;
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@ -1172,11 +1148,23 @@ void SoftFPU::FNCLEX(const X86::Instruction&)
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void SoftFPU::FNSTCW(const X86::Instruction& insn)
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{
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insn.modrm().write16(m_cpu, insn, shadow_wrap_as_initialized(m_fpu_cw));
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insn.modrm().write16(m_cpu, insn, shadow_wrap_as_initialized(m_fpu_cw.cw));
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}
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void SoftFPU::FLDCW(const X86::Instruction& insn)
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{
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m_fpu_cw = insn.modrm().read16(m_cpu, insn).value();
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m_fpu_cw.cw = insn.modrm().read16(m_cpu, insn).value();
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// Just let the host's x87 handle the rounding for us
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// We do not want to accedentally raise an FP-Exception on the host, so we
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// mask all exceptions
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AK::X87ControlWord temp = m_fpu_cw;
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temp.mask_invalid = 1;
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temp.mask_denorm = 1;
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temp.mask_zero_div = 1;
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temp.mask_overflow = 1;
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temp.mask_underflow = 1;
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temp.mask_precision = 1;
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AK::set_cw_x87(temp);
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}
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void SoftFPU::FNSTENV(const X86::Instruction& insn)
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@ -1204,7 +1192,7 @@ void SoftFPU::FNSTENV(const X86::Instruction& insn)
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auto address = insn.modrm().resolve(m_cpu, insn);
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m_cpu.write_memory16(address, shadow_wrap_as_initialized(m_fpu_cw));
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m_cpu.write_memory16(address, shadow_wrap_as_initialized(m_fpu_cw.cw));
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address.set_offset(address.offset() + 4);
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m_cpu.write_memory16(address, shadow_wrap_as_initialized(m_fpu_sw));
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address.set_offset(address.offset() + 4);
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@ -1227,7 +1215,17 @@ void SoftFPU::FLDENV(const X86::Instruction& insn)
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auto address = insn.modrm().resolve(m_cpu, insn);
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// FIXME: Shadow Values
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m_fpu_cw = m_cpu.read_memory16(address).value();
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m_fpu_cw.cw = m_cpu.read_memory16(address).value();
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// See note in FLDCW
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AK::X87ControlWord temp = m_fpu_cw;
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temp.mask_invalid = 1;
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temp.mask_denorm = 1;
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temp.mask_zero_div = 1;
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temp.mask_overflow = 1;
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temp.mask_underflow = 1;
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temp.mask_precision = 1;
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AK::set_cw_x87(temp);
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address.set_offset(address.offset() + 4);
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m_fpu_sw = m_cpu.read_memory16(address).value();
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address.set_offset(address.offset() + 4);
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