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Kernel: Support all Intel-defined CPUID feature flags for EAX=1
We're now able to detect all the regular CPUID feature flags from ECX/EDX for EAX=1 :^) None of the new ones are being used for anything yet, but they will show up in /proc/cpuinfo and subsequently lscpu and SystemMonitor. Note that I replaced the periods from the SSE 4.1 and 4.2 instructions with underscores, which matches the internal enum names, Linux's /proc/cpuinfo and the general pattern of replacing special characters with underscores to limit feature names to [a-z0-9_]. The enum member stringification has been moved to a new function for better re-usability and to avoid cluttering up Processor.cpp.
This commit is contained in:
Linus Groh
Andreas Kling
parent
bc7ec02a82
commit
6ca03b915e
5 changed files with 337 additions and 91 deletions
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@ -38,33 +38,88 @@ private:
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};
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u128,
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NX = CPUFeature(1u) << 0u,
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PAE = CPUFeature(1u) << 1u,
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PGE = CPUFeature(1u) << 2u,
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RDRAND = CPUFeature(1u) << 3u,
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RDSEED = CPUFeature(1u) << 4u,
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SMAP = CPUFeature(1u) << 5u,
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SMEP = CPUFeature(1u) << 6u,
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SSE = CPUFeature(1u) << 7u,
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TSC = CPUFeature(1u) << 8u,
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RDTSCP = CPUFeature(1u) << 9u,
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CONSTANT_TSC = CPUFeature(1u) << 10u,
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NONSTOP_TSC = CPUFeature(1u) << 11u,
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UMIP = CPUFeature(1u) << 12u,
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SEP = CPUFeature(1u) << 13u,
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SYSCALL = CPUFeature(1u) << 14u,
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MMX = CPUFeature(1u) << 15u,
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SSE2 = CPUFeature(1u) << 16u,
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SSE3 = CPUFeature(1u) << 17u,
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SSSE3 = CPUFeature(1u) << 18u,
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SSE4_1 = CPUFeature(1u) << 19u,
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SSE4_2 = CPUFeature(1u) << 20u,
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XSAVE = CPUFeature(1u) << 21u,
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AVX = CPUFeature(1u) << 22u,
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FXSR = CPUFeature(1u) << 23u,
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LM = CPUFeature(1u) << 24u,
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HYPERVISOR = CPUFeature(1u) << 25u,
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PAT = CPUFeature(1u) << 26u,
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__End = CPUFeature(1u) << 27u);
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/* EAX=1, ECX */ //
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SSE3 = CPUFeature(1u) << 0u, // Streaming SIMD Extensions 3
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PCLMULQDQ = CPUFeature(1u) << 1u, // PCLMULDQ Instruction
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DTES64 = CPUFeature(1u) << 2u, // 64-Bit Debug Store
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MONITOR = CPUFeature(1u) << 3u, // MONITOR/MWAIT Instructions
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DS_CPL = CPUFeature(1u) << 4u, // CPL Qualified Debug Store
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VMX = CPUFeature(1u) << 5u, // Virtual Machine Extensions
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SMX = CPUFeature(1u) << 6u, // Safer Mode Extensions
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EST = CPUFeature(1u) << 7u, // Enhanced Intel SpeedStep® Technology
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TM2 = CPUFeature(1u) << 8u, // Thermal Monitor 2
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SSSE3 = CPUFeature(1u) << 9u, // Supplemental Streaming SIMD Extensions 3
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CNXT_ID = CPUFeature(1u) << 10u, // L1 Context ID
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SDBG = CPUFeature(1u) << 11u, // Silicon Debug (IA32_DEBUG_INTERFACE MSR)
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FMA = CPUFeature(1u) << 12u, // Fused Multiply Add
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CX16 = CPUFeature(1u) << 13u, // CMPXCHG16B Instruction
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XTPR = CPUFeature(1u) << 14u, // xTPR Update Control
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PDCM = CPUFeature(1u) << 15u, // Perfmon and Debug Capability (IA32_PERF_CAPABILITIES MSR)
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/* ECX Bit 16 */ // Reserved
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PCID = CPUFeature(1u) << 17u, // Process Context Identifiers
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DCA = CPUFeature(1u) << 18u, // Direct Cache Access
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SSE4_1 = CPUFeature(1u) << 19u, // Streaming SIMD Extensions 4.1
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SSE4_2 = CPUFeature(1u) << 20u, // Streaming SIMD Extensions 4.2
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X2APIC = CPUFeature(1u) << 21u, // Extended xAPIC Support
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MOVBE = CPUFeature(1u) << 22u, // MOVBE Instruction
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POPCNT = CPUFeature(1u) << 23u, // POPCNT Instruction
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TSC_DEADLINE = CPUFeature(1u) << 24u, // Time Stamp Counter Deadline
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AES = CPUFeature(1u) << 25u, // AES Instruction Extensions
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XSAVE = CPUFeature(1u) << 26u, // XSAVE/XSTOR States
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OSXSAVE = CPUFeature(1u) << 27u, // OS-Enabled Extended State Management
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AVX = CPUFeature(1u) << 28u, // Advanced Vector Extensions
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F16C = CPUFeature(1u) << 29u, // 16-bit floating-point conversion instructions
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RDRAND = CPUFeature(1u) << 30u, // RDRAND Instruction
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HYPERVISOR = CPUFeature(1u) << 31u, // Hypervisor present (always zero on physical CPUs)
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/* EAX=1, EDX */ //
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FPU = CPUFeature(1u) << 32u, // Floating-point Unit On-Chip
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VME = CPUFeature(1u) << 33u, // Virtual Mode Extension
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DE = CPUFeature(1u) << 34u, // Debugging Extension
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PSE = CPUFeature(1u) << 35u, // Page Size Extension
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TSC = CPUFeature(1u) << 36u, // Time Stamp Counter
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MSR = CPUFeature(1u) << 37u, // Model Specific Registers
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PAE = CPUFeature(1u) << 38u, // Physical Address Extension
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MCE = CPUFeature(1u) << 39u, // Machine-Check Exception
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CX8 = CPUFeature(1u) << 40u, // CMPXCHG8 Instruction
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APIC = CPUFeature(1u) << 41u, // On-chip APIC Hardware
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/* EDX Bit 10 */ // Reserved
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SEP = CPUFeature(1u) << 43u, // Fast System Call
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MTRR = CPUFeature(1u) << 44u, // Memory Type Range Registers
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PGE = CPUFeature(1u) << 45u, // Page Global Enable
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MCA = CPUFeature(1u) << 46u, // Machine-Check Architecture
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CMOV = CPUFeature(1u) << 47u, // Conditional Move Instruction
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PAT = CPUFeature(1u) << 48u, // Page Attribute Table
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PSE36 = CPUFeature(1u) << 49u, // 36-bit Page Size Extension
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PSN = CPUFeature(1u) << 50u, // Processor serial number is present and enabled
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CLFLUSH = CPUFeature(1u) << 51u, // CLFLUSH Instruction
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/* EDX Bit 20 */ // Reserved
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DS = CPUFeature(1u) << 53u, // CLFLUSH Instruction
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ACPI = CPUFeature(1u) << 54u, // CLFLUSH Instruction
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MMX = CPUFeature(1u) << 55u, // CLFLUSH Instruction
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FXSR = CPUFeature(1u) << 56u, // CLFLUSH Instruction
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SSE = CPUFeature(1u) << 57u, // Streaming SIMD Extensions
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SSE2 = CPUFeature(1u) << 58u, // Streaming SIMD Extensions 2
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SS = CPUFeature(1u) << 59u, // Self-Snoop
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HTT = CPUFeature(1u) << 60u, // Multi-Threading
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TM = CPUFeature(1u) << 61u, // Thermal Monitor
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IA64 = CPUFeature(1u) << 62u, // IA64 processor emulating x86
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PBE = CPUFeature(1u) << 63u, // Pending Break Enable
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/* EAX=7, EBX */ //
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SMEP = CPUFeature(1u) << 64u, // Supervisor Mode Execution Protection
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RDSEED = CPUFeature(1u) << 65u, // RDSEED Instruction
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SMAP = CPUFeature(1u) << 66u, // Supervisor Mode Access Prevention
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/* EAX=7, ECX */ //
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UMIP = CPUFeature(1u) << 67u, // User-Mode Instruction Prevention
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/* EAX=80000001h, EDX */ //
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SYSCALL = CPUFeature(1u) << 68u, // SYSCALL/SYSRET Instructions
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NX = CPUFeature(1u) << 69u, // NX bit
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RDTSCP = CPUFeature(1u) << 70u, // RDTSCP Instruction
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LM = CPUFeature(1u) << 71u, // Long Mode
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/* EAX=80000007h, EDX */ //
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CONSTANT_TSC = CPUFeature(1u) << 72u, // Invariant TSC
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NONSTOP_TSC = CPUFeature(1u) << 73u, // Invariant TSC
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__End = CPUFeature(1u) << 127u);
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StringView cpu_feature_to_string_view(CPUFeature::Type const&);
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}
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