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https://github.com/RGBCube/serenity
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Kernel: Move i386.{cpp,h} => Arch/i386/CPU.{cpp,h}
There's a ton of work that would need to be done before we could spin up on another architecture, but let's at least try to separate things out a bit.
This commit is contained in:
Andreas Kling
parent
5bce004d84
commit
736092a087
20 changed files with 20 additions and 21 deletions
526
Kernel/Arch/i386/CPU.cpp
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526
Kernel/Arch/i386/CPU.cpp
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@ -0,0 +1,526 @@
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#include "Assertions.h"
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#include "IRQHandler.h"
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#include "PIC.h"
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#include "Process.h"
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#include "Scheduler.h"
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#include <AK/Types.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/KSyms.h>
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#include <Kernel/VM/MemoryManager.h>
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//#define PAGE_FAULT_DEBUG
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struct [[gnu::packed]] DescriptorTablePointer
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{
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word limit;
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void* address;
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};
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static DescriptorTablePointer s_idtr;
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static DescriptorTablePointer s_gdtr;
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static Descriptor s_idt[256];
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static Descriptor s_gdt[256];
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static IRQHandler* s_irq_handler[16];
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static Vector<word>* s_gdt_freelist;
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static word s_gdt_length;
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word gdt_alloc_entry()
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{
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ASSERT(s_gdt_freelist);
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ASSERT(!s_gdt_freelist->is_empty());
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return s_gdt_freelist->take_last();
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}
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void gdt_free_entry(word entry)
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{
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s_gdt_freelist->append(entry);
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}
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extern "C" void handle_irq();
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extern "C" void asm_irq_entry();
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asm(
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".globl asm_irq_entry\n"
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"asm_irq_entry: \n"
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" pusha\n"
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" pushw %ds\n"
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" pushw %es\n"
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" pushw %ss\n"
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" pushw %ss\n"
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" popw %ds\n"
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" popw %es\n"
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" call handle_irq\n"
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" popw %es\n"
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" popw %ds\n"
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" popa\n"
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" iret\n");
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#define EH_ENTRY(ec) \
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extern "C" void exception_##ec##_handler(RegisterDumpWithExceptionCode&); \
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extern "C" void exception_##ec##_entry(); \
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asm( \
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".globl exception_" #ec "_entry\n" \
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"exception_" #ec "_entry: \n" \
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" pusha\n" \
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" pushw %ds\n" \
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" pushw %es\n" \
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" pushw %fs\n" \
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" pushw %gs\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" popw %ds\n" \
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" popw %es\n" \
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" popw %fs\n" \
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" popw %gs\n" \
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" mov %esp, %eax\n" \
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" call exception_" #ec "_handler\n" \
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" popw %gs\n" \
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" popw %gs\n" \
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" popw %fs\n" \
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" popw %es\n" \
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" popw %ds\n" \
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" popa\n" \
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" add $0x4, %esp\n" \
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" iret\n");
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#define EH_ENTRY_NO_CODE(ec) \
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extern "C" void exception_##ec##_handler(RegisterDump&); \
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extern "C" void exception_##ec##_entry(); \
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asm( \
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".globl exception_" #ec "_entry\n" \
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"exception_" #ec "_entry: \n" \
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" pusha\n" \
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" pushw %ds\n" \
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" pushw %es\n" \
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" pushw %fs\n" \
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" pushw %gs\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" pushw %ss\n" \
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" popw %ds\n" \
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" popw %es\n" \
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" popw %fs\n" \
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" popw %gs\n" \
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" mov %esp, %eax\n" \
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" call exception_" #ec "_handler\n" \
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" popw %gs\n" \
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" popw %gs\n" \
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" popw %fs\n" \
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" popw %es\n" \
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" popw %ds\n" \
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" popa\n" \
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" iret\n");
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template<typename DumpType>
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static void dump(const DumpType& regs)
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{
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word ss;
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dword esp;
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if (!current || current->process().is_ring0()) {
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ss = regs.ds;
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esp = regs.esp;
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} else {
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ss = regs.ss_if_crossRing;
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esp = regs.esp_if_crossRing;
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}
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if constexpr (IsSame<DumpType, RegisterDumpWithExceptionCode>::value) {
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kprintf("exception code: %w\n", regs.exception_code);
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}
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kprintf(" pc=%w:%x ds=%w es=%w fs=%w gs=%w\n", regs.cs, regs.eip, regs.ds, regs.es, regs.fs, regs.gs);
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kprintf(" stk=%w:%x\n", ss, esp);
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if (current)
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kprintf("kstk=%w:%x, base=%x, sigbase=%x\n", current->tss().ss0, current->tss().esp0, current->kernel_stack_base(), current->kernel_stack_for_signal_handler_base());
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kprintf("eax=%x ebx=%x ecx=%x edx=%x\n", regs.eax, regs.ebx, regs.ecx, regs.edx);
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kprintf("ebp=%x esp=%x esi=%x edi=%x\n", regs.ebp, esp, regs.esi, regs.edi);
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if (current && current->process().validate_read((void*)regs.eip, 8)) {
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byte* codeptr = (byte*)regs.eip;
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kprintf("code: %b %b %b %b %b %b %b %b\n",
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codeptr[0],
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codeptr[1],
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codeptr[2],
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codeptr[3],
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codeptr[4],
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codeptr[5],
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codeptr[6],
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codeptr[7]);
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}
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}
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// 6: Invalid Opcode
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EH_ENTRY_NO_CODE(6);
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void exception_6_handler(RegisterDump& regs)
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{
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if (!current) {
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kprintf("#UD with !current\n");
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hang();
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}
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kprintf("%s Illegal instruction: %s(%u)\n",
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current->process().is_ring0() ? "Kernel" : "Process",
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current->process().name().characters(),
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current->pid());
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dump(regs);
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dump_backtrace();
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if (current->process().is_ring0()) {
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kprintf("Oh shit, we've crashed in ring 0 :(\n");
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hang();
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}
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current->process().crash(SIGILL);
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}
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// 7: FPU not available exception
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EH_ENTRY_NO_CODE(7);
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void exception_7_handler(RegisterDump& regs)
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{
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(void)regs;
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asm volatile("clts");
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if (g_last_fpu_thread == current)
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return;
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if (g_last_fpu_thread) {
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asm volatile("fxsave %0"
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: "=m"(g_last_fpu_thread->fpu_state()));
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} else {
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asm volatile("fnclex");
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}
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g_last_fpu_thread = current;
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if (current->has_used_fpu()) {
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asm volatile("fxrstor %0" ::"m"(current->fpu_state()));
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} else {
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asm volatile("fninit");
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current->set_has_used_fpu(true);
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}
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#ifdef FPU_EXCEPTION_DEBUG
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kprintf("%s FPU not available exception: %u(%s)\n", current->process().is_ring0() ? "Kernel" : "Process", current->pid(), current->process().name().characters());
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dump(regs);
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#endif
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}
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// 0: Divide error
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EH_ENTRY_NO_CODE(0);
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void exception_0_handler(RegisterDump& regs)
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{
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kprintf("%s Division by zero: %s(%u)\n",
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current->process().is_ring0() ? "Kernel" : "User",
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current->process().name().characters(),
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current->pid());
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dump(regs);
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if (current->process().is_ring0()) {
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kprintf("Oh shit, we've crashed in ring 0 :(\n");
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hang();
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}
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current->process().crash(SIGFPE);
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}
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// 13: General Protection Fault
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EH_ENTRY(13);
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void exception_13_handler(RegisterDumpWithExceptionCode& regs)
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{
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kprintf("%s GPF: %u(%s)\n", current->process().is_ring0() ? "Kernel" : "User", current->pid(), current->process().name().characters());
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dump(regs);
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if (current->process().is_ring0()) {
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kprintf("Oh shit, we've crashed in ring 0 :(\n");
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hang();
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}
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current->process().crash();
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}
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// 14: Page Fault
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EH_ENTRY(14);
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void exception_14_handler(RegisterDumpWithExceptionCode& regs)
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{
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ASSERT(current);
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dword faultAddress;
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asm("movl %%cr2, %%eax"
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: "=a"(faultAddress));
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dword fault_page_directory;
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asm("movl %%cr3, %%eax"
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: "=a"(fault_page_directory));
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#ifdef PAGE_FAULT_DEBUG
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dbgprintf("%s(%u): ring%u %s page fault in PD=%x, %s L%x\n",
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current->process().name().characters(),
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current->pid(),
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regs.cs & 3,
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regs.exception_code & 1 ? "PV" : "NP",
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fault_page_directory,
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regs.exception_code & 2 ? "write" : "read",
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faultAddress);
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#endif
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#ifdef PAGE_FAULT_DEBUG
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dump(regs);
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#endif
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auto response = MM.handle_page_fault(PageFault(regs.exception_code, VirtualAddress(faultAddress)));
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if (response == PageFaultResponse::ShouldCrash) {
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kprintf("%s(%u:%u) unrecoverable page fault, %s vaddr=%p\n",
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current->process().name().characters(),
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current->pid(),
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current->tid(),
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regs.exception_code & 2 ? "write" : "read",
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faultAddress);
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dump(regs);
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current->process().crash();
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} else if (response == PageFaultResponse::Continue) {
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#ifdef PAGE_FAULT_DEBUG
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dbgprintf("Continuing after resolved page fault\n");
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#endif
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} else {
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ASSERT_NOT_REACHED();
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}
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}
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#define EH(i, msg) \
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static void _exception##i() \
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{ \
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kprintf(msg "\n"); \
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dword cr0, cr2, cr3, cr4; \
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asm("movl %%cr0, %%eax" \
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: "=a"(cr0)); \
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asm("movl %%cr2, %%eax" \
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: "=a"(cr2)); \
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asm("movl %%cr3, %%eax" \
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: "=a"(cr3)); \
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asm("movl %%cr4, %%eax" \
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: "=a"(cr4)); \
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kprintf("CR0=%x CR2=%x CR3=%x CR4=%x\n", cr0, cr2, cr3, cr4); \
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hang(); \
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}
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EH(1, "Debug exception")
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EH(2, "Unknown error")
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EH(3, "Breakpoint")
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EH(4, "Overflow")
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EH(5, "Bounds check")
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EH(8, "Double fault")
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EH(9, "Coprocessor segment overrun")
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EH(10, "Invalid TSS")
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EH(11, "Segment not present")
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EH(12, "Stack exception")
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EH(15, "Unknown error")
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EH(16, "Coprocessor error")
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static void write_raw_gdt_entry(word selector, dword low, dword high)
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{
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word i = (selector & 0xfffc) >> 3;
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s_gdt[i].low = low;
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s_gdt[i].high = high;
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if (i > s_gdt_length)
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s_gdtr.limit = (s_gdt_length + 1) * 8 - 1;
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}
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void write_gdt_entry(word selector, Descriptor& descriptor)
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{
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write_raw_gdt_entry(selector, descriptor.low, descriptor.high);
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}
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Descriptor& get_gdt_entry(word selector)
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{
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word i = (selector & 0xfffc) >> 3;
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return *(Descriptor*)(&s_gdt[i]);
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}
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void flush_gdt()
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{
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s_gdtr.address = s_gdt;
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s_gdtr.limit = (s_gdt_length * 8) - 1;
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asm("lgdt %0" ::"m"(s_gdtr)
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: "memory");
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}
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void gdt_init()
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{
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s_gdt_length = 5;
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s_gdt_freelist = new Vector<word>();
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s_gdt_freelist->ensure_capacity(256);
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for (size_t i = s_gdt_length; i < 256; ++i)
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s_gdt_freelist->append(i * 8);
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s_gdt_length = 256;
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s_gdtr.address = s_gdt;
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s_gdtr.limit = (s_gdt_length * 8) - 1;
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write_raw_gdt_entry(0x0000, 0x00000000, 0x00000000);
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write_raw_gdt_entry(0x0008, 0x0000ffff, 0x00cf9a00);
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write_raw_gdt_entry(0x0010, 0x0000ffff, 0x00cf9200);
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write_raw_gdt_entry(0x0018, 0x0000ffff, 0x00cffa00);
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write_raw_gdt_entry(0x0020, 0x0000ffff, 0x00cff200);
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flush_gdt();
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asm volatile(
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"mov %%ax, %%ds\n"
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"mov %%ax, %%es\n"
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"mov %%ax, %%fs\n"
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"mov %%ax, %%gs\n"
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"mov %%ax, %%ss\n" ::"a"(0x10)
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: "memory");
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// Make sure CS points to the kernel code descriptor.
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asm volatile(
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"ljmpl $0x8, $sanity\n"
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"sanity:\n");
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}
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static void unimp_trap()
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{
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kprintf("Unhandled IRQ.");
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hang();
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}
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void register_irq_handler(byte irq, IRQHandler& handler)
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{
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ASSERT(!s_irq_handler[irq]);
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s_irq_handler[irq] = &handler;
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register_interrupt_handler(IRQ_VECTOR_BASE + irq, asm_irq_entry);
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}
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void unregister_irq_handler(byte irq, IRQHandler& handler)
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{
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ASSERT(s_irq_handler[irq] == &handler);
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s_irq_handler[irq] = nullptr;
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}
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void register_interrupt_handler(byte index, void (*f)())
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{
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s_idt[index].low = 0x00080000 | LSW((f));
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s_idt[index].high = ((dword)(f)&0xffff0000) | 0x8e00;
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flush_idt();
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}
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void register_user_callable_interrupt_handler(byte index, void (*f)())
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{
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s_idt[index].low = 0x00080000 | LSW((f));
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s_idt[index].high = ((dword)(f)&0xffff0000) | 0xef00;
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flush_idt();
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}
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void flush_idt()
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{
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asm("lidt %0" ::"m"(s_idtr));
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}
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/* If an 8259 gets cranky, it'll generate a spurious IRQ7.
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* ATM I don't have a clear grasp on when/why this happens,
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* so I ignore them and assume it makes no difference.
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*/
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extern "C" void irq7_handler();
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asm(
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".globl irq7_handler \n"
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"irq7_handler: \n"
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" iret\n");
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void idt_init()
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{
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s_idtr.address = s_idt;
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s_idtr.limit = 0x100 * 8 - 1;
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for (byte i = 0xff; i > 0x10; --i)
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register_interrupt_handler(i, unimp_trap);
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register_interrupt_handler(0x00, exception_0_entry);
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register_interrupt_handler(0x01, _exception1);
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register_interrupt_handler(0x02, _exception2);
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register_interrupt_handler(0x03, _exception3);
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register_interrupt_handler(0x04, _exception4);
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register_interrupt_handler(0x05, _exception5);
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register_interrupt_handler(0x06, exception_6_entry);
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register_interrupt_handler(0x07, exception_7_entry);
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register_interrupt_handler(0x08, _exception8);
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register_interrupt_handler(0x09, _exception9);
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register_interrupt_handler(0x0a, _exception10);
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register_interrupt_handler(0x0b, _exception11);
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register_interrupt_handler(0x0c, _exception12);
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register_interrupt_handler(0x0d, exception_13_entry);
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register_interrupt_handler(0x0e, exception_14_entry);
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register_interrupt_handler(0x0f, _exception15);
|
||||
register_interrupt_handler(0x10, _exception16);
|
||||
|
||||
register_interrupt_handler(0x57, irq7_handler);
|
||||
|
||||
for (byte i = 0; i < 16; ++i) {
|
||||
s_irq_handler[i] = nullptr;
|
||||
}
|
||||
|
||||
flush_idt();
|
||||
}
|
||||
|
||||
void load_task_register(word selector)
|
||||
{
|
||||
asm("ltr %0" ::"r"(selector));
|
||||
}
|
||||
|
||||
void handle_irq()
|
||||
{
|
||||
word isr = PIC::get_isr();
|
||||
if (!isr) {
|
||||
kprintf("Spurious IRQ\n");
|
||||
return;
|
||||
}
|
||||
|
||||
byte irq = 0;
|
||||
for (byte i = 0; i < 16; ++i) {
|
||||
if (i == 2)
|
||||
continue;
|
||||
if (isr & (1 << i)) {
|
||||
irq = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (s_irq_handler[irq])
|
||||
s_irq_handler[irq]->handle_irq();
|
||||
PIC::eoi(irq);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
void __assertion_failed(const char* msg, const char* file, unsigned line, const char* func)
|
||||
{
|
||||
asm volatile("cli");
|
||||
kprintf("ASSERTION FAILED: %s\n%s:%u in %s\n", msg, file, line, func);
|
||||
dump_backtrace();
|
||||
asm volatile("hlt");
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void sse_init()
|
||||
{
|
||||
asm volatile(
|
||||
"mov %cr0, %eax\n"
|
||||
"andl $0xfffffffb, %eax\n"
|
||||
"orl $0x2, %eax\n"
|
||||
"mov %eax, %cr0\n"
|
||||
"mov %cr4, %eax\n"
|
||||
"orl $0x600, %eax\n"
|
||||
"mov %eax, %cr4\n");
|
||||
}
|
||||
325
Kernel/Arch/i386/CPU.h
Normal file
325
Kernel/Arch/i386/CPU.h
Normal file
|
|
@ -0,0 +1,325 @@
|
|||
#pragma once
|
||||
|
||||
#include <Kernel/VirtualAddress.h>
|
||||
#include <Kernel/kstdio.h>
|
||||
|
||||
#define PAGE_SIZE 4096
|
||||
#define PAGE_MASK 0xfffff000
|
||||
|
||||
struct [[gnu::packed]] TSS32
|
||||
{
|
||||
word backlink, __blh;
|
||||
dword esp0;
|
||||
word ss0, __ss0h;
|
||||
dword esp1;
|
||||
word ss1, __ss1h;
|
||||
dword esp2;
|
||||
word ss2, __ss2h;
|
||||
dword cr3, eip, eflags;
|
||||
dword eax, ecx, edx, ebx, esp, ebp, esi, edi;
|
||||
word es, __esh;
|
||||
word cs, __csh;
|
||||
word ss, __ssh;
|
||||
word ds, __dsh;
|
||||
word fs, __fsh;
|
||||
word gs, __gsh;
|
||||
word ldt, __ldth;
|
||||
word trace, iomapbase;
|
||||
};
|
||||
|
||||
union [[gnu::packed]] Descriptor
|
||||
{
|
||||
struct {
|
||||
word limit_lo;
|
||||
word base_lo;
|
||||
byte base_hi;
|
||||
byte type : 4;
|
||||
byte descriptor_type : 1;
|
||||
byte dpl : 2;
|
||||
byte segment_present : 1;
|
||||
byte limit_hi : 4;
|
||||
byte : 1;
|
||||
byte zero : 1;
|
||||
byte operation_size : 1;
|
||||
byte granularity : 1;
|
||||
byte base_hi2;
|
||||
};
|
||||
struct {
|
||||
dword low;
|
||||
dword high;
|
||||
};
|
||||
|
||||
enum Type {
|
||||
Invalid = 0,
|
||||
AvailableTSS_16bit = 0x1,
|
||||
LDT = 0x2,
|
||||
BusyTSS_16bit = 0x3,
|
||||
CallGate_16bit = 0x4,
|
||||
TaskGate = 0x5,
|
||||
InterruptGate_16bit = 0x6,
|
||||
TrapGate_16bit = 0x7,
|
||||
AvailableTSS_32bit = 0x9,
|
||||
BusyTSS_32bit = 0xb,
|
||||
CallGate_32bit = 0xc,
|
||||
InterruptGate_32bit = 0xe,
|
||||
TrapGate_32bit = 0xf,
|
||||
};
|
||||
|
||||
void set_base(void* b)
|
||||
{
|
||||
base_lo = (dword)(b)&0xffff;
|
||||
base_hi = ((dword)(b) >> 16) & 0xff;
|
||||
base_hi2 = ((dword)(b) >> 24) & 0xff;
|
||||
}
|
||||
|
||||
void set_limit(dword l)
|
||||
{
|
||||
limit_lo = (dword)l & 0xffff;
|
||||
limit_hi = ((dword)l >> 16) & 0xff;
|
||||
}
|
||||
};
|
||||
|
||||
class IRQHandler;
|
||||
|
||||
void gdt_init();
|
||||
void idt_init();
|
||||
void sse_init();
|
||||
void register_interrupt_handler(byte number, void (*f)());
|
||||
void register_user_callable_interrupt_handler(byte number, void (*f)());
|
||||
void register_irq_handler(byte number, IRQHandler&);
|
||||
void unregister_irq_handler(byte number, IRQHandler&);
|
||||
void flush_idt();
|
||||
void flush_gdt();
|
||||
void load_task_register(word selector);
|
||||
word gdt_alloc_entry();
|
||||
void gdt_free_entry(word);
|
||||
Descriptor& get_gdt_entry(word selector);
|
||||
void write_gdt_entry(word selector, Descriptor&);
|
||||
|
||||
[[noreturn]] static inline void hang()
|
||||
{
|
||||
asm volatile("cli; hlt");
|
||||
for (;;) {
|
||||
}
|
||||
}
|
||||
|
||||
#define LSW(x) ((dword)(x)&0xFFFF)
|
||||
#define MSW(x) (((dword)(x) >> 16) & 0xFFFF)
|
||||
#define LSB(x) ((x)&0xFF)
|
||||
#define MSB(x) (((x) >> 8) & 0xFF)
|
||||
|
||||
#define cli() asm volatile("cli" :: \
|
||||
: "memory")
|
||||
#define sti() asm volatile("sti" :: \
|
||||
: "memory")
|
||||
#define memory_barrier() asm volatile("" :: \
|
||||
: "memory")
|
||||
|
||||
inline dword cpu_cr3()
|
||||
{
|
||||
dword cr3;
|
||||
asm volatile("movl %%cr3, %%eax"
|
||||
: "=a"(cr3));
|
||||
return cr3;
|
||||
}
|
||||
|
||||
inline dword cpu_flags()
|
||||
{
|
||||
dword flags;
|
||||
asm volatile(
|
||||
"pushf\n"
|
||||
"pop %0\n"
|
||||
: "=rm"(flags)::"memory");
|
||||
return flags;
|
||||
}
|
||||
|
||||
inline bool are_interrupts_enabled()
|
||||
{
|
||||
return cpu_flags() & 0x200;
|
||||
}
|
||||
|
||||
class InterruptFlagSaver {
|
||||
public:
|
||||
InterruptFlagSaver()
|
||||
{
|
||||
m_flags = cpu_flags();
|
||||
}
|
||||
|
||||
~InterruptFlagSaver()
|
||||
{
|
||||
if (m_flags & 0x200)
|
||||
sti();
|
||||
else
|
||||
cli();
|
||||
}
|
||||
|
||||
private:
|
||||
dword m_flags;
|
||||
};
|
||||
|
||||
class InterruptDisabler {
|
||||
public:
|
||||
InterruptDisabler()
|
||||
{
|
||||
m_flags = cpu_flags();
|
||||
cli();
|
||||
}
|
||||
|
||||
~InterruptDisabler()
|
||||
{
|
||||
if (m_flags & 0x200)
|
||||
sti();
|
||||
}
|
||||
|
||||
private:
|
||||
dword m_flags;
|
||||
};
|
||||
|
||||
/* Map IRQ0-15 @ ISR 0x50-0x5F */
|
||||
#define IRQ_VECTOR_BASE 0x50
|
||||
|
||||
struct PageFaultFlags {
|
||||
enum Flags {
|
||||
NotPresent = 0x00,
|
||||
ProtectionViolation = 0x01,
|
||||
Read = 0x00,
|
||||
Write = 0x02,
|
||||
UserMode = 0x04,
|
||||
SupervisorMode = 0x00,
|
||||
InstructionFetch = 0x08,
|
||||
};
|
||||
};
|
||||
|
||||
class PageFault {
|
||||
public:
|
||||
PageFault(word code, VirtualAddress vaddr)
|
||||
: m_code(code)
|
||||
, m_vaddr(vaddr)
|
||||
{
|
||||
}
|
||||
|
||||
VirtualAddress vaddr() const { return m_vaddr; }
|
||||
word code() const { return m_code; }
|
||||
|
||||
bool is_not_present() const { return (m_code & 1) == PageFaultFlags::NotPresent; }
|
||||
bool is_protection_violation() const { return (m_code & 1) == PageFaultFlags::ProtectionViolation; }
|
||||
bool is_read() const { return (m_code & 2) == PageFaultFlags::Read; }
|
||||
bool is_write() const { return (m_code & 2) == PageFaultFlags::Write; }
|
||||
bool is_user() const { return (m_code & 4) == PageFaultFlags::UserMode; }
|
||||
bool is_supervisor() const { return (m_code & 4) == PageFaultFlags::SupervisorMode; }
|
||||
bool is_instruction_fetch() const { return (m_code & 8) == PageFaultFlags::InstructionFetch; }
|
||||
|
||||
private:
|
||||
word m_code;
|
||||
VirtualAddress m_vaddr;
|
||||
};
|
||||
|
||||
struct [[gnu::packed]] RegisterDump
|
||||
{
|
||||
word ss;
|
||||
word gs;
|
||||
word fs;
|
||||
word es;
|
||||
word ds;
|
||||
dword edi;
|
||||
dword esi;
|
||||
dword ebp;
|
||||
dword esp;
|
||||
dword ebx;
|
||||
dword edx;
|
||||
dword ecx;
|
||||
dword eax;
|
||||
dword eip;
|
||||
word cs;
|
||||
word __csPadding;
|
||||
dword eflags;
|
||||
dword esp_if_crossRing;
|
||||
word ss_if_crossRing;
|
||||
};
|
||||
|
||||
struct [[gnu::packed]] RegisterDumpWithExceptionCode
|
||||
{
|
||||
word ss;
|
||||
word gs;
|
||||
word fs;
|
||||
word es;
|
||||
word ds;
|
||||
dword edi;
|
||||
dword esi;
|
||||
dword ebp;
|
||||
dword esp;
|
||||
dword ebx;
|
||||
dword edx;
|
||||
dword ecx;
|
||||
dword eax;
|
||||
word exception_code;
|
||||
word __exception_code_padding;
|
||||
dword eip;
|
||||
word cs;
|
||||
word __csPadding;
|
||||
dword eflags;
|
||||
dword esp_if_crossRing;
|
||||
word ss_if_crossRing;
|
||||
};
|
||||
|
||||
struct [[gnu::aligned(16)]] FPUState
|
||||
{
|
||||
byte buffer[512];
|
||||
};
|
||||
|
||||
inline constexpr dword page_base_of(dword address)
|
||||
{
|
||||
return address & 0xfffff000;
|
||||
}
|
||||
|
||||
class CPUID {
|
||||
public:
|
||||
CPUID(dword function) { asm volatile("cpuid"
|
||||
: "=a"(m_eax), "=b"(m_ebx), "=c"(m_ecx), "=d"(m_edx)
|
||||
: "a"(function), "c"(0)); }
|
||||
dword eax() const { return m_eax; }
|
||||
dword ebx() const { return m_ebx; }
|
||||
dword ecx() const { return m_ecx; }
|
||||
dword edx() const { return m_edx; }
|
||||
|
||||
private:
|
||||
dword m_eax { 0xffffffff };
|
||||
dword m_ebx { 0xffffffff };
|
||||
dword m_ecx { 0xffffffff };
|
||||
dword m_edx { 0xffffffff };
|
||||
};
|
||||
|
||||
inline void read_tsc(dword& lsw, dword& msw)
|
||||
{
|
||||
asm volatile("rdtsc"
|
||||
: "=d"(msw), "=a"(lsw));
|
||||
}
|
||||
|
||||
struct Stopwatch {
|
||||
union SplitQword {
|
||||
struct {
|
||||
uint32_t lsw;
|
||||
uint32_t msw;
|
||||
};
|
||||
uint64_t qw { 0 };
|
||||
};
|
||||
|
||||
public:
|
||||
Stopwatch(const char* name)
|
||||
: m_name(name)
|
||||
{
|
||||
read_tsc(m_start.lsw, m_start.msw);
|
||||
}
|
||||
|
||||
~Stopwatch()
|
||||
{
|
||||
SplitQword end;
|
||||
read_tsc(end.lsw, end.msw);
|
||||
uint64_t diff = end.qw - m_start.qw;
|
||||
dbgprintf("Stopwatch(%s): %Q ticks\n", m_name, diff);
|
||||
}
|
||||
|
||||
private:
|
||||
const char* m_name { nullptr };
|
||||
SplitQword m_start;
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue