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Kernel: Move i386.{cpp,h} => Arch/i386/CPU.{cpp,h}
There's a ton of work that would need to be done before we could spin up on another architecture, but let's at least try to separate things out a bit.
This commit is contained in:
Andreas Kling
parent
5bce004d84
commit
736092a087
20 changed files with 20 additions and 21 deletions
325
Kernel/Arch/i386/CPU.h
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325
Kernel/Arch/i386/CPU.h
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#pragma once
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#include <Kernel/VirtualAddress.h>
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#include <Kernel/kstdio.h>
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#define PAGE_SIZE 4096
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#define PAGE_MASK 0xfffff000
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struct [[gnu::packed]] TSS32
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{
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word backlink, __blh;
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dword esp0;
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word ss0, __ss0h;
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dword esp1;
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word ss1, __ss1h;
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dword esp2;
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word ss2, __ss2h;
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dword cr3, eip, eflags;
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dword eax, ecx, edx, ebx, esp, ebp, esi, edi;
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word es, __esh;
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word cs, __csh;
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word ss, __ssh;
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word ds, __dsh;
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word fs, __fsh;
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word gs, __gsh;
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word ldt, __ldth;
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word trace, iomapbase;
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};
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union [[gnu::packed]] Descriptor
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{
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struct {
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word limit_lo;
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word base_lo;
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byte base_hi;
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byte type : 4;
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byte descriptor_type : 1;
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byte dpl : 2;
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byte segment_present : 1;
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byte limit_hi : 4;
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byte : 1;
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byte zero : 1;
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byte operation_size : 1;
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byte granularity : 1;
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byte base_hi2;
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};
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struct {
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dword low;
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dword high;
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};
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enum Type {
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Invalid = 0,
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AvailableTSS_16bit = 0x1,
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LDT = 0x2,
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BusyTSS_16bit = 0x3,
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CallGate_16bit = 0x4,
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TaskGate = 0x5,
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InterruptGate_16bit = 0x6,
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TrapGate_16bit = 0x7,
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AvailableTSS_32bit = 0x9,
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BusyTSS_32bit = 0xb,
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CallGate_32bit = 0xc,
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InterruptGate_32bit = 0xe,
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TrapGate_32bit = 0xf,
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};
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void set_base(void* b)
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{
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base_lo = (dword)(b)&0xffff;
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base_hi = ((dword)(b) >> 16) & 0xff;
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base_hi2 = ((dword)(b) >> 24) & 0xff;
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}
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void set_limit(dword l)
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{
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limit_lo = (dword)l & 0xffff;
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limit_hi = ((dword)l >> 16) & 0xff;
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}
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};
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class IRQHandler;
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void gdt_init();
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void idt_init();
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void sse_init();
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void register_interrupt_handler(byte number, void (*f)());
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void register_user_callable_interrupt_handler(byte number, void (*f)());
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void register_irq_handler(byte number, IRQHandler&);
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void unregister_irq_handler(byte number, IRQHandler&);
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void flush_idt();
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void flush_gdt();
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void load_task_register(word selector);
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word gdt_alloc_entry();
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void gdt_free_entry(word);
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Descriptor& get_gdt_entry(word selector);
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void write_gdt_entry(word selector, Descriptor&);
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[[noreturn]] static inline void hang()
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{
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asm volatile("cli; hlt");
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for (;;) {
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}
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}
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#define LSW(x) ((dword)(x)&0xFFFF)
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#define MSW(x) (((dword)(x) >> 16) & 0xFFFF)
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#define LSB(x) ((x)&0xFF)
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#define MSB(x) (((x) >> 8) & 0xFF)
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#define cli() asm volatile("cli" :: \
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: "memory")
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#define sti() asm volatile("sti" :: \
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: "memory")
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#define memory_barrier() asm volatile("" :: \
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: "memory")
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inline dword cpu_cr3()
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{
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dword cr3;
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asm volatile("movl %%cr3, %%eax"
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: "=a"(cr3));
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return cr3;
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}
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inline dword cpu_flags()
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{
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dword flags;
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asm volatile(
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"pushf\n"
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"pop %0\n"
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: "=rm"(flags)::"memory");
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return flags;
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}
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inline bool are_interrupts_enabled()
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{
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return cpu_flags() & 0x200;
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}
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class InterruptFlagSaver {
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public:
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InterruptFlagSaver()
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{
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m_flags = cpu_flags();
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}
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~InterruptFlagSaver()
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{
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if (m_flags & 0x200)
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sti();
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else
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cli();
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}
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private:
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dword m_flags;
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};
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class InterruptDisabler {
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public:
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InterruptDisabler()
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{
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m_flags = cpu_flags();
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cli();
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}
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~InterruptDisabler()
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{
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if (m_flags & 0x200)
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sti();
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}
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private:
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dword m_flags;
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};
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/* Map IRQ0-15 @ ISR 0x50-0x5F */
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#define IRQ_VECTOR_BASE 0x50
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struct PageFaultFlags {
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enum Flags {
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NotPresent = 0x00,
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ProtectionViolation = 0x01,
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Read = 0x00,
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Write = 0x02,
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UserMode = 0x04,
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SupervisorMode = 0x00,
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InstructionFetch = 0x08,
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};
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};
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class PageFault {
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public:
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PageFault(word code, VirtualAddress vaddr)
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: m_code(code)
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, m_vaddr(vaddr)
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{
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}
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VirtualAddress vaddr() const { return m_vaddr; }
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word code() const { return m_code; }
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bool is_not_present() const { return (m_code & 1) == PageFaultFlags::NotPresent; }
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bool is_protection_violation() const { return (m_code & 1) == PageFaultFlags::ProtectionViolation; }
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bool is_read() const { return (m_code & 2) == PageFaultFlags::Read; }
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bool is_write() const { return (m_code & 2) == PageFaultFlags::Write; }
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bool is_user() const { return (m_code & 4) == PageFaultFlags::UserMode; }
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bool is_supervisor() const { return (m_code & 4) == PageFaultFlags::SupervisorMode; }
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bool is_instruction_fetch() const { return (m_code & 8) == PageFaultFlags::InstructionFetch; }
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private:
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word m_code;
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VirtualAddress m_vaddr;
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};
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struct [[gnu::packed]] RegisterDump
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{
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word ss;
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word gs;
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word fs;
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word es;
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word ds;
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dword edi;
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dword esi;
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dword ebp;
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dword esp;
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dword ebx;
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dword edx;
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dword ecx;
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dword eax;
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dword eip;
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word cs;
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word __csPadding;
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dword eflags;
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dword esp_if_crossRing;
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word ss_if_crossRing;
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};
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struct [[gnu::packed]] RegisterDumpWithExceptionCode
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{
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word ss;
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word gs;
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word fs;
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word es;
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word ds;
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dword edi;
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dword esi;
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dword ebp;
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dword esp;
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dword ebx;
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dword edx;
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dword ecx;
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dword eax;
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word exception_code;
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word __exception_code_padding;
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dword eip;
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word cs;
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word __csPadding;
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dword eflags;
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dword esp_if_crossRing;
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word ss_if_crossRing;
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};
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struct [[gnu::aligned(16)]] FPUState
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{
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byte buffer[512];
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};
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inline constexpr dword page_base_of(dword address)
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{
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return address & 0xfffff000;
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}
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class CPUID {
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public:
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CPUID(dword function) { asm volatile("cpuid"
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: "=a"(m_eax), "=b"(m_ebx), "=c"(m_ecx), "=d"(m_edx)
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: "a"(function), "c"(0)); }
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dword eax() const { return m_eax; }
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dword ebx() const { return m_ebx; }
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dword ecx() const { return m_ecx; }
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dword edx() const { return m_edx; }
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private:
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dword m_eax { 0xffffffff };
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dword m_ebx { 0xffffffff };
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dword m_ecx { 0xffffffff };
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dword m_edx { 0xffffffff };
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};
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inline void read_tsc(dword& lsw, dword& msw)
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{
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asm volatile("rdtsc"
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: "=d"(msw), "=a"(lsw));
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}
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struct Stopwatch {
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union SplitQword {
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struct {
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uint32_t lsw;
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uint32_t msw;
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};
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uint64_t qw { 0 };
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};
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public:
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Stopwatch(const char* name)
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: m_name(name)
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{
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read_tsc(m_start.lsw, m_start.msw);
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}
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~Stopwatch()
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{
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SplitQword end;
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read_tsc(end.lsw, end.msw);
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uint64_t diff = end.qw - m_start.qw;
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dbgprintf("Stopwatch(%s): %Q ticks\n", m_name, diff);
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}
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private:
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const char* m_name { nullptr };
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SplitQword m_start;
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};
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