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UserspaceEmulator: Implement the SHL family of instructions
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bfacb9583a
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1 changed files with 83 additions and 9 deletions
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@ -379,6 +379,34 @@ static T op_shr(SoftCPU& cpu, T data, u8 steps)
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return result;
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return result;
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}
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}
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template<typename T>
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static T op_shl(SoftCPU& cpu, T data, u8 steps)
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{
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if (steps == 0)
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return data;
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u32 result = 0;
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u32 new_flags = 0;
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if constexpr (sizeof(T) == 4)
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asm volatile("shll %%cl, %%eax\n" ::"a"(data), "c"(steps));
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else if constexpr (sizeof(T) == 2)
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asm volatile("shlw %%cl, %%ax\n" ::"a"(data), "c"(steps));
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else if constexpr (sizeof(T) == 1)
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asm volatile("shlb %%cl, %%al\n" ::"a"(data), "c"(steps));
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asm volatile(
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"mov %%eax, %%ebx\n"
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: "=b"(result));
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asm volatile(
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"pushf\n"
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"pop %%eax"
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: "=a"(new_flags));
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cpu.set_flags_oszapc(new_flags);
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return result;
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}
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template<bool update_dest, typename Op>
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template<bool update_dest, typename Op>
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void SoftCPU::generic_AL_imm8(Op op, const X86::Instruction& insn)
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void SoftCPU::generic_AL_imm8(Op op, const X86::Instruction& insn)
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{
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{
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@ -1143,15 +1171,61 @@ void SoftCPU::SHLD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM32_reg32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM32_reg32_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHL_RM16_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHL_RM16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHL_RM16_1(const X86::Instruction& insn)
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void SoftCPU::SHL_RM16_imm8(const X86::Instruction&) { TODO(); }
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{
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void SoftCPU::SHL_RM32_1(const X86::Instruction&) { TODO(); }
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auto data = insn.modrm().read16(*this, insn);
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void SoftCPU::SHL_RM32_CL(const X86::Instruction&) { TODO(); }
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insn.modrm().write16(*this, insn, op_shl(*this, data, 1));
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void SoftCPU::SHL_RM32_imm8(const X86::Instruction&) { TODO(); }
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}
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void SoftCPU::SHL_RM8_1(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHL_RM8_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHL_RM16_CL(const X86::Instruction& insn)
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void SoftCPU::SHL_RM8_imm8(const X86::Instruction&) { TODO(); }
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{
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auto data = insn.modrm().read16(*this, insn);
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insn.modrm().write16(*this, insn, op_shl(*this, data, cl()));
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}
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void SoftCPU::SHL_RM16_imm8(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read16(*this, insn);
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insn.modrm().write16(*this, insn, op_shl(*this, data, insn.imm8()));
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}
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void SoftCPU::SHL_RM32_1(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read32(*this, insn);
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insn.modrm().write32(*this, insn, op_shl(*this, data, 1));
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}
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void SoftCPU::SHL_RM32_CL(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read32(*this, insn);
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insn.modrm().write32(*this, insn, op_shl(*this, data, cl()));
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}
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void SoftCPU::SHL_RM32_imm8(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read32(*this, insn);
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insn.modrm().write32(*this, insn, op_shl(*this, data, insn.imm8()));
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}
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void SoftCPU::SHL_RM8_1(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read8(*this, insn);
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insn.modrm().write8(*this, insn, op_shl(*this, data, 1));
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}
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void SoftCPU::SHL_RM8_CL(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read8(*this, insn);
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insn.modrm().write8(*this, insn, op_shl(*this, data, cl()));
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}
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void SoftCPU::SHL_RM8_imm8(const X86::Instruction& insn)
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{
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auto data = insn.modrm().read8(*this, insn);
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insn.modrm().write8(*this, insn, op_shl(*this, data, insn.imm8()));
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}
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void SoftCPU::SHRD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
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