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Kernel/aarch64: Set correct ExecutionMode of PageFault
Adds a helper to aarch64/Registers.h to factor out the exception class encoding.
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2 changed files with 6 additions and 2 deletions
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@ -70,8 +70,7 @@ static PageFault page_fault_from_exception_syndrome_register(VirtualAddress faul
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fault.set_access((esr_el1.ISS & (1 << 6)) == (1 << 6) ? PageFault::Access::Write : PageFault::Access::Read);
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fault.set_access((esr_el1.ISS & (1 << 6)) == (1 << 6) ? PageFault::Access::Write : PageFault::Access::Read);
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// FIXME: Set correct mode
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fault.set_mode(Aarch64::exception_class_is_data_or_instruction_abort_from_lower_exception_level(esr_el1.EC) ? ExecutionMode::User : ExecutionMode::Kernel);
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fault.set_mode(ExecutionMode::Kernel);
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if (Aarch64::exception_class_is_instruction_abort(esr_el1.EC))
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if (Aarch64::exception_class_is_instruction_abort(esr_el1.EC))
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fault.set_instruction_fetch(true);
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fault.set_instruction_fetch(true);
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@ -1167,6 +1167,11 @@ static inline bool exception_class_is_instruction_abort(u8 exception_class)
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return exception_class == 0x20 || exception_class == 0x21;
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return exception_class == 0x20 || exception_class == 0x21;
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}
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}
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static inline bool exception_class_is_data_or_instruction_abort_from_lower_exception_level(u8 exception_class)
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{
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return exception_class == 0x20 || exception_class == 0x24;
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}
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// D17.2.37 ESR_EL1, Exception Syndrome Register (EL1)
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// D17.2.37 ESR_EL1, Exception Syndrome Register (EL1)
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// ISS encoding for an exception from a Data Abort
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// ISS encoding for an exception from a Data Abort
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// DFSC, bits [5:0]
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// DFSC, bits [5:0]
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