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Kernel/aarch64: Remove tpidr_el0 from RegisterState
In the next commit, this register will be populated by directly writing to it, instead of using the RegisterState mechanism.
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parent
cff6af9f75
commit
7d0917f50b
4 changed files with 6 additions and 14 deletions
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@ -42,7 +42,6 @@ void dump_registers(RegisterState const& regs)
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dbgln("Saved Program Status: (NZCV({:#b}) DAIF({:#b}) M({:#b})) / 0x{:x}", ((regs.spsr_el1 >> 28) & 0b1111), ((regs.spsr_el1 >> 6) & 0b1111), regs.spsr_el1 & 0b1111, regs.spsr_el1);
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dbgln("Exception Link Register: 0x{:x}", regs.elr_el1);
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dbgln("Software Thread ID: 0x{:x}", regs.tpidr_el0);
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dbgln("Stack Pointer (EL0): 0x{:x}", regs.sp_el0);
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dbgln(" x0={:p} x1={:p} x2={:p} x3={:p} x4={:p}", regs.x[0], regs.x[1], regs.x[2], regs.x[3], regs.x[4]);
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@ -291,7 +291,6 @@ FlatPtr Processor::init_context(Thread& thread, bool leave_crit)
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eretframe.x[30] = FlatPtr(&exit_kernel_thread);
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eretframe.elr_el1 = thread_regs.elr_el1;
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eretframe.sp_el0 = thread_regs.sp_el0;
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eretframe.tpidr_el0 = 0; // FIXME: Correctly initialize this when aarch64 has support for thread local storage.
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eretframe.spsr_el1 = thread_regs.spsr_el1;
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// Push a TrapFrame onto the stack
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@ -16,11 +16,10 @@ VALIDATE_IS_AARCH64()
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namespace Kernel {
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struct RegisterState {
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u64 x[31]; // Saved general purpose registers
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u64 spsr_el1; // Save Processor Status Register, EL1
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u64 elr_el1; // Exception Link Register, EL1
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u64 tpidr_el0; // EL0 thread ID
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u64 sp_el0; // EL0 stack pointer
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u64 x[31]; // Saved general purpose registers
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u64 spsr_el1; // Save Processor Status Register, EL1
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u64 elr_el1; // Exception Link Register, EL1
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u64 sp_el0; // EL0 stack pointer
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FlatPtr userspace_sp() const { return sp_el0; }
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void set_userspace_sp(FlatPtr value)
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@ -6,11 +6,10 @@
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.section .text.vector_table
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#define REGISTER_STATE_SIZE 272
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#define REGISTER_STATE_SIZE 264
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#define SPSR_EL1_SLOT (31 * 8)
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#define ELR_EL1_SLOT (32 * 8)
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#define TPIDR_EL0_SLOT (33 * 8)
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#define SP_EL0_SLOT (34 * 8)
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#define SP_EL0_SLOT (33 * 8)
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// Vector Table Entry macro. Each entry is aligned at 128 bytes, meaning we have
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// at most that many instructions.
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@ -58,8 +57,6 @@
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str x0, [sp, #SPSR_EL1_SLOT]
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mrs x0, elr_el1
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str x0, [sp, #ELR_EL1_SLOT]
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mrs x0, tpidr_el0
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str x0, [sp, #TPIDR_EL0_SLOT]
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mrs x0, sp_el0
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str x0, [sp, #SP_EL0_SLOT]
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@ -83,8 +80,6 @@
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msr spsr_el1, x0
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ldr x0, [sp, #ELR_EL1_SLOT]
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msr elr_el1, x0
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ldr x0, [sp, #TPIDR_EL0_SLOT]
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msr tpidr_el0, x0
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ldr x0, [sp, #SP_EL0_SLOT]
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msr sp_el0, x0
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