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Kernel/aarch64: Remove tpidr_el0 from RegisterState

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In the next commit, this register will be populated by directly writing
to it, instead of using the RegisterState mechanism.
This commit is contained in:
Timon Kruiper 2023-02-15 19:36:34 +01:00 • committed by Jelle Raaijmakers
parent cff6af9f75
commit 7d0917f50b
4 changed files with 6 additions and 14 deletions
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9
Kernel/Arch/aarch64/vector_table.S
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@ -6,11 +6,10 @@
.section .text.vector_table
#define REGISTER_STATE_SIZE 272
#define REGISTER_STATE_SIZE 264
#define SPSR_EL1_SLOT (31 * 8)
#define ELR_EL1_SLOT (32 * 8)
#define TPIDR_EL0_SLOT (33 * 8)
#define SP_EL0_SLOT (34 * 8)
#define SP_EL0_SLOT (33 * 8)
// Vector Table Entry macro. Each entry is aligned at 128 bytes, meaning we have
// at most that many instructions.
@ -58,8 +57,6 @@
str x0, [sp, #SPSR_EL1_SLOT]
mrs x0, elr_el1
str x0, [sp, #ELR_EL1_SLOT]
mrs x0, tpidr_el0
str x0, [sp, #TPIDR_EL0_SLOT]
mrs x0, sp_el0
str x0, [sp, #SP_EL0_SLOT]
@ -83,8 +80,6 @@
msr spsr_el1, x0
ldr x0, [sp, #ELR_EL1_SLOT]
msr elr_el1, x0
ldr x0, [sp, #TPIDR_EL0_SLOT]
msr tpidr_el0, x0
ldr x0, [sp, #SP_EL0_SLOT]
msr sp_el0, x0