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Kernel/IntelGraphics: Move pipe management to the Transcoder class
It became apparent to me that future generations of the Intel graphics chipset utilize the same register set as part of the Transcoder register set. Therefore, it should be included now in the Transcoder class.
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parent
2def16a3d2
commit
8042ae43c3
7 changed files with 95 additions and 122 deletions
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@ -147,12 +147,14 @@ ErrorOr<void> IntelDisplayConnectorGroup::initialize_gen4_connectors()
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// NOTE: Just assume we will need one Gen4 "transcoder"
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// NOTE: Main block of registers starting at HorizontalTotalA register (0x60000)
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auto transcoder_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x60000);
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// NOTE: Main block of Pipe registers starting at PipeA_DSL register (0x70000)
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auto pipe_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x70000);
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// NOTE: DPLL registers starting at DPLLDivisorA0 register (0x6040)
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auto dpll_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x6040);
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// NOTE: DPLL A control registers starting at 0x6014 (DPLL A Control register),
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// DPLL A Multiplier is at 0x601C, between them (at 0x6018) there is the DPLL B Control register.
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auto dpll_control_registers_paddr = m_mmio_first_region.pci_bar_paddr.offset(0x6014);
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m_transcoders[0] = TRY(IntelAnalogDisplayTranscoder::create_with_physical_addresses(transcoder_registers_paddr, dpll_registers_paddr, dpll_control_registers_paddr));
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m_transcoders[0] = TRY(IntelAnalogDisplayTranscoder::create_with_physical_addresses(transcoder_registers_paddr, pipe_registers_paddr, dpll_registers_paddr, dpll_control_registers_paddr));
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m_planes[0] = TRY(IntelG33DisplayPlane::create_with_physical_address(m_mmio_first_region.pci_bar_paddr.offset(0x70180)));
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Array<u8, 128> crt_edid_bytes {};
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{
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@ -299,29 +301,6 @@ u32 IntelDisplayConnectorGroup::read_from_analog_output_register(AnalogOutputReg
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return value;
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}
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void IntelDisplayConnectorGroup::write_to_global_generation_register(IntelGraphics::GlobalGenerationRegister index, u32 value)
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{
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write_to_general_register(to_underlying(index), value);
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}
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u32 IntelDisplayConnectorGroup::read_from_global_generation_register(IntelGraphics::GlobalGenerationRegister index) const
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{
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u32 value = read_from_general_register(to_underlying(index));
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return value;
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}
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bool IntelDisplayConnectorGroup::pipe_a_enabled() const
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{
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VERIFY(m_control_lock.is_locked());
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return read_from_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeAConf) & (1 << 30);
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}
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bool IntelDisplayConnectorGroup::pipe_b_enabled() const
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{
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VERIFY(m_control_lock.is_locked());
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return read_from_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeBConf) & (1 << 30);
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}
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static size_t compute_dac_multiplier(size_t pixel_clock_in_khz)
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{
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Intel native graphics: Pixel clock is {} KHz", pixel_clock_in_khz);
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@ -351,8 +330,7 @@ bool IntelDisplayConnectorGroup::set_crt_resolution(DisplayConnector::ModeSettin
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disable_dac_output();
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MUST(m_planes[0]->disable({}));
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disable_pipe_a();
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disable_pipe_b();
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MUST(m_transcoders[0]->disable_pipe({}));
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MUST(m_transcoders[0]->disable_dpll({}));
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disable_vga_emulation();
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@ -362,8 +340,8 @@ bool IntelDisplayConnectorGroup::set_crt_resolution(DisplayConnector::ModeSettin
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MUST(m_transcoders[0]->enable_dpll_without_vga({}));
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MUST(m_transcoders[0]->set_mode_setting_timings({}, mode_setting));
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VERIFY(!pipe_a_enabled());
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enable_pipe_a();
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VERIFY(!m_transcoders[0]->pipe_enabled({}));
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MUST(m_transcoders[0]->enable_pipe({}));
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MUST(m_planes[0]->set_plane_settings({}, m_mmio_second_region.pci_bar_paddr, IntelDisplayPlane::PipeSelect::PipeA, mode_setting.horizontal_active));
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MUST(m_planes[0]->enable({}));
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enable_dac_output();
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@ -371,74 +349,6 @@ bool IntelDisplayConnectorGroup::set_crt_resolution(DisplayConnector::ModeSettin
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return true;
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}
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bool IntelDisplayConnectorGroup::wait_for_enabled_pipe_a(size_t milliseconds_timeout) const
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{
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size_t current_time = 0;
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while (current_time < milliseconds_timeout) {
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if (pipe_a_enabled())
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return true;
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microseconds_delay(1000);
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current_time++;
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}
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return false;
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}
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bool IntelDisplayConnectorGroup::wait_for_disabled_pipe_a(size_t milliseconds_timeout) const
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{
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size_t current_time = 0;
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while (current_time < milliseconds_timeout) {
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if (!pipe_a_enabled())
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return true;
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microseconds_delay(1000);
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current_time++;
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}
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return false;
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}
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bool IntelDisplayConnectorGroup::wait_for_disabled_pipe_b(size_t milliseconds_timeout) const
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{
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size_t current_time = 0;
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while (current_time < milliseconds_timeout) {
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if (!pipe_b_enabled())
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return true;
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microseconds_delay(1000);
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current_time++;
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}
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return false;
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}
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void IntelDisplayConnectorGroup::disable_pipe_a()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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write_to_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeAConf, 0);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe A");
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wait_for_disabled_pipe_a(100);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe A - done.");
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}
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void IntelDisplayConnectorGroup::disable_pipe_b()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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write_to_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeAConf, 0);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe B");
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wait_for_disabled_pipe_b(100);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe B - done.");
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}
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void IntelDisplayConnectorGroup::enable_pipe_a()
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{
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VERIFY(m_control_lock.is_locked());
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VERIFY(m_modeset_lock.is_locked());
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VERIFY(!(read_from_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeAConf) & (1 << 31)));
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VERIFY(!(read_from_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeAConf) & (1 << 30)));
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write_to_global_generation_register(IntelGraphics::GlobalGenerationRegister::PipeAConf, (1 << 31) | (1 << 24));
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dbgln_if(INTEL_GRAPHICS_DEBUG, "enabling Pipe A");
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// FIXME: Seems like my video card is buggy and doesn't set the enabled bit (bit 30)!!
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wait_for_enabled_pipe_a(100);
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dbgln_if(INTEL_GRAPHICS_DEBUG, "enabling Pipe A - done.");
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}
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void IntelDisplayConnectorGroup::disable_dac_output()
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{
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VERIFY(m_control_lock.is_locked());
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