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Kernel/IntelGraphics: Move pipe management to the Transcoder class

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It became apparent to me that future generations of the Intel graphics
chipset utilize the same register set as part of the Transcoder register
set. Therefore, it should be included now in the Transcoder class.
This commit is contained in:
Liav A 2022-04-01 12:52:49 +03:00 • committed by Andrew Kaster
parent 2def16a3d2
commit 8042ae43c3
7 changed files with 95 additions and 122 deletions
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55
Kernel/Graphics/Intel/Transcoder/DisplayTranscoder.cpp
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@ -4,13 +4,15 @@
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <Kernel/Arch/Delay.h>
#include <Kernel/Graphics/Intel/Transcoder/DisplayTranscoder.h>
#include <Kernel/PhysicalAddress.h>
namespace Kernel {
IntelDisplayTranscoder::IntelDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile> registers_mapping)
IntelDisplayTranscoder::IntelDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile> registers_mapping, Memory::TypedMapping<PipeRegisters volatile> pipe_registers_mapping)
: m_transcoder_registers(move(registers_mapping))
, m_pipe_registers(move(pipe_registers_mapping))
{
}
@ -54,4 +56,55 @@ ErrorOr<void> IntelDisplayTranscoder::set_mode_setting_timings(Badge<IntelDispla
return {};
}
ErrorOr<void> IntelDisplayTranscoder::disable_pipe(Badge<IntelDisplayConnectorGroup>)
{
SpinlockLocker locker(m_access_lock);
m_pipe_registers->pipe_configuration = 0;
m_shadow_registers.pipe_conf = 0;
dbgln_if(INTEL_GRAPHICS_DEBUG, "Disabling Pipe");
size_t milliseconds_elapsed = 0;
while (milliseconds_elapsed < 100) {
u32 value = m_pipe_registers->pipe_configuration;
if (!(value & (1 << 30)))
return {};
microseconds_delay(1000);
milliseconds_elapsed++;
}
return Error::from_errno(EBUSY);
}
ErrorOr<void> IntelDisplayTranscoder::enable_pipe(Badge<IntelDisplayConnectorGroup>)
{
SpinlockLocker locker(m_access_lock);
u32 value = m_pipe_registers->pipe_configuration;
// Note: Just verify these are not already enabled...
if ((value & (1 << 30)) && (value & (1 << 31)))
return {};
// Note: Set the pipe configuration register with these bits:
// 1. Bit 31 - to enable the Pipe
// 2. Bit 24 - to enable Gamma Unit Mode to 10 bit Gamma mode.
// 3. Bits 21-23 are set to zero to indicate Progressive mode (non Interlaced mode)
// 4. Bits 18 and 19 are set to zero to indicate Normal operations of assigned
// Cursor and Display planes.
m_pipe_registers->pipe_configuration = (1 << 31) | (1 << 24);
m_shadow_registers.pipe_conf = (1 << 31) | (1 << 24);
dbgln_if(INTEL_GRAPHICS_DEBUG, "Enabling Pipe");
size_t milliseconds_elapsed = 0;
while (milliseconds_elapsed < 100) {
u32 value = m_pipe_registers->pipe_configuration;
if ((value & (1 << 30)))
return {};
microseconds_delay(1000);
milliseconds_elapsed++;
}
// FIXME: Seems like my video card is buggy and doesn't set the enabled bit (bit 30)!!
return {};
}
bool IntelDisplayTranscoder::pipe_enabled(Badge<IntelDisplayConnectorGroup>) const
{
SpinlockLocker locker(m_access_lock);
u32 value = m_pipe_registers->pipe_configuration;
return (value & (1 << 30));
}
}