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https://github.com/RGBCube/serenity
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Kernel: Run clang-format on files
Let's rip off the band-aid
This commit is contained in:
Shannon Booth
Andreas Kling
parent
d0629d0a8c
commit
81adefef27
25 changed files with 2992 additions and 2995 deletions
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@ -54,177 +54,177 @@ namespace Kernel {
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namespace APIC {
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class ICRReg {
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u32 m_reg { 0 };
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class ICRReg {
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u32 m_reg { 0 };
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public:
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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SMI = 0x2,
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NMI = 0x4,
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INIT = 0x5,
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StartUp = 0x6,
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};
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enum DestinationMode {
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Physical = 0x0,
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Logical = 0x0,
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};
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enum Level {
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DeAssert = 0x0,
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Assert = 0x1
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};
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enum class TriggerMode {
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Edge = 0x0,
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Level = 0x1,
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};
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enum DestinationShorthand {
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NoShorthand = 0x0,
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Self = 0x1,
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AllIncludingSelf = 0x2,
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AllExcludingSelf = 0x3,
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};
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
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: m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
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{
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}
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u32 low() const { return m_reg; }
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u32 high() const { return 0; }
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public:
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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SMI = 0x2,
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NMI = 0x4,
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INIT = 0x5,
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StartUp = 0x6,
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};
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enum DestinationMode {
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Physical = 0x0,
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Logical = 0x0,
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};
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enum Level {
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DeAssert = 0x0,
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Assert = 0x1
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};
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enum class TriggerMode {
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Edge = 0x0,
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Level = 0x1,
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};
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enum DestinationShorthand {
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NoShorthand = 0x0,
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Self = 0x1,
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AllIncludingSelf = 0x2,
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AllExcludingSelf = 0x3,
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};
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static volatile u8* g_apic_base = nullptr;
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static PhysicalAddress get_base()
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destination)
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: m_reg(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination << 18))
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{
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u32 lo, hi;
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MSR msr(APIC_BASE_MSR);
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msr.get(lo, hi);
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return PhysicalAddress(lo & 0xfffff000);
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}
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static void set_base(const PhysicalAddress& base)
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{
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u32 hi = 0;
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u32 lo = base.get() | 0x800;
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MSR msr(APIC_BASE_MSR);
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msr.set(lo, hi);
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}
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u32 low() const { return m_reg; }
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u32 high() const { return 0; }
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};
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static void write_register(u32 offset, u32 value)
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{
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auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Write Access", Region::Access::Read | Region::Access::Write, false, true);
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auto* lapic = (volatile u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
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*lapic = value;
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}
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static volatile u8* g_apic_base = nullptr;
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static u32 read_register(u32 offset)
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{
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auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Read Access", Region::Access::Read, false, true);
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auto* lapic = (volatile u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
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return *lapic;
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}
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static PhysicalAddress get_base()
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{
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u32 lo, hi;
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MSR msr(APIC_BASE_MSR);
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msr.get(lo, hi);
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return PhysicalAddress(lo & 0xfffff000);
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}
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static void write_icr(const ICRReg& icr)
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{
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write_register(APIC_REG_ICR_HIGH, icr.high());
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write_register(APIC_REG_ICR_LOW, icr.low());
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}
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static void set_base(const PhysicalAddress& base)
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{
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u32 hi = 0;
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u32 lo = base.get() | 0x800;
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MSR msr(APIC_BASE_MSR);
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msr.set(lo, hi);
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}
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static void write_register(u32 offset, u32 value)
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{
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auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Write Access", Region::Access::Read | Region::Access::Write, false, true);
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auto* lapic = (volatile u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
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*lapic = value;
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}
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static u32 read_register(u32 offset)
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{
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auto lapic_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of((u32)g_apic_base)), PAGE_SIZE, "LAPIC Read Access", Region::Access::Read, false, true);
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auto* lapic = (volatile u32*)lapic_region->vaddr().offset(offset_in_page((u32)g_apic_base)).offset(offset).as_ptr();
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return *lapic;
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}
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static void write_icr(const ICRReg& icr)
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{
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write_register(APIC_REG_ICR_HIGH, icr.high());
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write_register(APIC_REG_ICR_LOW, icr.low());
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}
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#define APIC_LVT_MASKED (1 << 16)
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#define APIC_LVT_TRIGGER_LEVEL (1 << 14)
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#define APIC_LVT(iv, dm) ((iv & 0xff) | ((dm & 0x7) << 8))
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asm(
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".globl apic_ap_start \n"
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".type apic_ap_start, @function \n"
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"apic_ap_start: \n"
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".set begin_apic_ap_start, . \n"
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" jmp apic_ap_start\n" // TODO: implement
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".set end_apic_ap_start, . \n"
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"\n"
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".globl apic_ap_start_size \n"
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"apic_ap_start_size: \n"
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".word end_apic_ap_start - begin_apic_ap_start \n");
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asm(
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".globl apic_ap_start \n"
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".type apic_ap_start, @function \n"
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"apic_ap_start: \n"
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".set begin_apic_ap_start, . \n"
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" jmp apic_ap_start\n" // TODO: implement
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".set end_apic_ap_start, . \n"
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"\n"
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".globl apic_ap_start_size \n"
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"apic_ap_start_size: \n"
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".word end_apic_ap_start - begin_apic_ap_start \n");
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extern "C" void apic_ap_start(void);
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extern "C" u16 apic_ap_start_size;
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extern "C" void apic_ap_start(void);
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extern "C" u16 apic_ap_start_size;
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void eoi()
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{
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write_register(APIC_REG_EOI, 0x0);
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}
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void eoi()
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{
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write_register(APIC_REG_EOI, 0x0);
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}
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bool init()
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{
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if (!MSR::have())
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return false;
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bool init()
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{
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if (!MSR::have())
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return false;
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// check if we support local apic
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CPUID id(1);
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if ((id.edx() & (1 << 9)) == 0)
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return false;
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// check if we support local apic
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CPUID id(1);
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if ((id.edx() & (1 << 9)) == 0)
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return false;
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PhysicalAddress apic_base = get_base();
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klog() << "Initializing APIC, base: " << apic_base;
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set_base(apic_base);
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PhysicalAddress apic_base = get_base();
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klog() << "Initializing APIC, base: " << apic_base;
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set_base(apic_base);
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g_apic_base = apic_base.as_ptr();
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g_apic_base = apic_base.as_ptr();
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return true;
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}
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return true;
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}
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void enable_bsp()
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{
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// FIXME: Ensure this method can only be executed by the BSP.
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enable(0);
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}
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void enable_bsp()
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{
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// FIXME: Ensure this method can only be executed by the BSP.
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enable(0);
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}
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void enable(u32 cpu)
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{
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klog() << "Enabling local APIC for cpu #" << cpu;
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void enable(u32 cpu)
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{
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klog() << "Enabling local APIC for cpu #" << cpu;
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// dummy read, apparently to avoid a bug in old CPUs.
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read_register(APIC_REG_SIV);
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// set spurious interrupt vector
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write_register(APIC_REG_SIV, IRQ_APIC_SPURIOUS | 0x100);
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// dummy read, apparently to avoid a bug in old CPUs.
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read_register(APIC_REG_SIV);
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// set spurious interrupt vector
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write_register(APIC_REG_SIV, IRQ_APIC_SPURIOUS | 0x100);
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// local destination mode (flat mode)
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write_register(APIC_REG_DF, 0xf0000000);
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// local destination mode (flat mode)
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write_register(APIC_REG_DF, 0xf0000000);
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// set destination id (note that this limits it to 8 cpus)
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write_register(APIC_REG_LD, 0);
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// set destination id (note that this limits it to 8 cpus)
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write_register(APIC_REG_LD, 0);
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SpuriousInterruptHandler::initialize(IRQ_APIC_SPURIOUS);
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SpuriousInterruptHandler::initialize(IRQ_APIC_SPURIOUS);
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write_register(APIC_REG_LVT_TIMER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_THERMAL, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_LINT0, APIC_LVT(0, 7) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_LINT1, APIC_LVT(0, 0) | APIC_LVT_TRIGGER_LEVEL);
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write_register(APIC_REG_LVT_ERR, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_TIMER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_THERMAL, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_LINT0, APIC_LVT(0, 7) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_LINT1, APIC_LVT(0, 0) | APIC_LVT_TRIGGER_LEVEL);
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write_register(APIC_REG_LVT_ERR, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_TPR, 0);
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write_register(APIC_REG_TPR, 0);
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if (cpu != 0) {
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static volatile u32 foo = 0;
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if (cpu != 0) {
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static volatile u32 foo = 0;
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// INIT
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write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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// INIT
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write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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for (foo = 0; foo < 0x800000; foo++)
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; // TODO: 10 millisecond delay
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for (foo = 0; foo < 0x800000; foo++)
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; // TODO: 10 millisecond delay
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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for (foo = 0; foo < 0x80000; foo++)
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; // TODO: 200 microsecond delay
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}
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for (foo = 0; foo < 0x80000; foo++)
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; // TODO: 200 microsecond delay
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}
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}
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}
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}
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