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Kernel/Storage: Move IDE bus master handling code into a separate class
If the user requests to force PIO mode, we just create IDEChannel objects which are capable of sending PIO commands only. However, if the user doesn't force PIO mode, we create BMIDEChannel objects, which are sending DMA commands. This change is somewhat simplifying the code, so each class is supporting its type of operation - PIO or DMA. The PATADiskDevice should not care if DMA is enabled or not. Later on, we could write an IDEChannel class for UDMA modes, that are available and documented on Intel specifications for their IDE controllers.
This commit is contained in:
Liav A
Andreas Kling
parent
dfb6b296cf
commit
833a6bd047
7 changed files with 341 additions and 163 deletions
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@ -27,7 +27,6 @@
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#include <AK/ByteBuffer.h>
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#include <AK/Singleton.h>
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#include <AK/StringView.h>
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#include <Kernel/FileSystem/ProcFS.h>
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#include <Kernel/IO.h>
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#include <Kernel/Process.h>
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#include <Kernel/Storage/ATA.h>
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@ -45,9 +44,9 @@ namespace Kernel {
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#define PCI_Mass_Storage_Class 0x1
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#define PCI_IDE_Controller_Subclass 0x1
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UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(const IDEController& controller, IOAddressGroup io_group, ChannelType type, bool force_pio)
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UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(const IDEController& controller, IOAddressGroup io_group, ChannelType type)
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{
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return adopt(*new IDEChannel(controller, io_group, type, force_pio));
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return adopt(*new IDEChannel(controller, io_group, type));
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}
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RefPtr<StorageDevice> IDEChannel::master_device() const
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@ -60,7 +59,7 @@ RefPtr<StorageDevice> IDEChannel::slave_device() const
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return m_slave;
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}
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type, bool force_pio)
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UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type)
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: IRQHandler(type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ)
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, m_channel_type(type)
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, m_io_group(io_group)
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@ -69,15 +68,16 @@ UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddre
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disable_irq();
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// FIXME: The device may not be capable of DMA.
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m_dma_enabled.resource() = !force_pio;
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ProcFS::add_sys_bool("ide_dma", m_dma_enabled);
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initialize(force_pio);
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dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base: {}", channel_type_string(), m_io_group.bus_master_base());
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m_parent_controller->enable_pin_based_interrupts();
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detect_disks();
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// Note: calling to detect_disks could generate an interrupt, clear it if that's the case
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clear_pending_interrupts();
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enable_irq();
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}
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void IDEChannel::clear_pending_interrupts() const
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@ -89,7 +89,7 @@ UNMAP_AFTER_INIT IDEChannel::~IDEChannel()
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{
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}
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void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool use_dma, bool is_slave, u16 capabilities)
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void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool is_slave, u16 capabilities)
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{
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ScopedSpinLock lock(m_request_lock);
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@ -97,20 +97,12 @@ void IDEChannel::start_request(AsyncBlockDeviceRequest& request, bool use_dma, b
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m_current_request = &request;
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m_current_request_block_index = 0;
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m_current_request_uses_dma = use_dma;
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m_current_request_flushing_cache = false;
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if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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if (use_dma)
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ata_read_sectors_with_dma(is_slave, capabilities);
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else
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ata_read_sectors(is_slave, capabilities);
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} else {
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if (use_dma)
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ata_write_sectors_with_dma(is_slave, capabilities);
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else
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ata_write_sectors(is_slave, capabilities);
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}
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if (request.request_type() == AsyncBlockDeviceRequest::Read)
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ata_read_sectors(is_slave, capabilities);
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else
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ata_write_sectors(is_slave, capabilities);
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}
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void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult result)
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@ -130,46 +122,11 @@ void IDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult resu
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auto& request = *m_current_request;
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m_current_request = nullptr;
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if (m_current_request_uses_dma) {
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if (result == AsyncDeviceRequest::Success) {
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if (request.request_type() == AsyncBlockDeviceRequest::Read) {
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if (!request.write_to_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
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lock.unlock();
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request.complete(AsyncDeviceRequest::MemoryFault);
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return;
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}
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}
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// I read somewhere that this may trigger a cache flush so let's do it.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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}
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}
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lock.unlock();
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request.complete(result);
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});
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}
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UNMAP_AFTER_INIT void IDEChannel::initialize(bool force_pio)
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{
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m_parent_controller->enable_pin_based_interrupts();
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dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
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dbgln_if(PATA_DEBUG, "IDEChannel: {} bus master base: {}", channel_type_string(), m_io_group.bus_master_base());
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if (force_pio) {
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dbgln("IDEChannel: Requested to force PIO mode; not setting up DMA");
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return;
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}
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// Let's try to set up DMA transfers.
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PCI::enable_bus_mastering(m_parent_controller->pci_address());
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m_prdt_page = MM.allocate_supervisor_physical_page();
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prdt().end_of_table = 0x8000;
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m_dma_buffer_page = MM.allocate_supervisor_physical_page();
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}
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static void print_ide_status(u8 status)
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{
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dbgln("IDEChannel: print_ide_status: DRQ={} BSY={}, DRDY={}, DSC={}, DF={}, CORR={}, IDX={}, ERR={}",
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@ -251,10 +208,6 @@ void IDEChannel::handle_irq(const RegisterState&)
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return;
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}
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m_device_error = 0;
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if (m_current_request_uses_dma) {
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complete_current_request(AsyncDeviceRequest::Success);
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return;
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}
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// Now schedule reading/writing the buffer as soon as we leave the irq handler.
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// This is important so that we can safely access the buffers, which could
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@ -404,7 +357,7 @@ UNMAP_AFTER_INIT void IDEChannel::detect_disks()
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}
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}
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void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8 block_count, u16 capabilities, bool use_dma)
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void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8 block_count, u16 capabilities)
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{
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LBAMode lba_mode;
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u8 head = 0;
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@ -439,48 +392,17 @@ void IDEChannel::ata_access(Direction direction, bool slave_request, u64 lba, u8
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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if (lba_mode != LBAMode::FortyEightBit) {
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if (use_dma)
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA : ATA_CMD_WRITE_DMA);
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else
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO : ATA_CMD_WRITE_PIO);
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} else {
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if (use_dma)
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_DMA_EXT : ATA_CMD_WRITE_DMA_EXT);
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else
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO_EXT : ATA_CMD_WRITE_PIO_EXT);
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}
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send_ata_io_command(lba_mode, direction);
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enable_irq();
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}
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void IDEChannel::ata_read_sectors_with_dma(bool slave_request, u16 capabilities)
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void IDEChannel::send_ata_io_command(LBAMode lba_mode, Direction direction) const
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{
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auto& request = *m_current_request;
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auto lba = request.block_index();
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_read_sectors_with_dma ({} x {})", lba, request.block_count());
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prdt().offset = m_dma_buffer_page->paddr();
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prdt().size = 512 * request.block_count();
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VERIFY(prdt().size <= PAGE_SIZE);
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// Stop bus master
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m_io_group.bus_master_base().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().offset(4).out(m_prdt_page->paddr().get());
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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// Set transfer direction
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m_io_group.bus_master_base().out<u8>(0x8);
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ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities, true);
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// Start bus master
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m_io_group.bus_master_base().out<u8>(0x9);
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if (lba_mode != LBAMode::FortyEightBit) {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO : ATA_CMD_WRITE_PIO);
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} else {
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m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(direction == Direction::Read ? ATA_CMD_READ_PIO_EXT : ATA_CMD_WRITE_PIO_EXT);
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}
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}
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bool IDEChannel::ata_do_read_sector()
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@ -511,38 +433,7 @@ void IDEChannel::ata_read_sectors(bool slave_request, u16 capabilities)
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auto lba = request.block_index();
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dbgln_if(PATA_DEBUG, "IDEChannel: Reading {} sector(s) @ LBA {}", request.block_count(), lba);
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ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities, false);
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}
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void IDEChannel::ata_write_sectors_with_dma(bool slave_request, u16 capabilities)
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{
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auto& request = *m_current_request;
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auto lba = request.block_index();
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dbgln_if(PATA_DEBUG, "IDEChannel::ata_write_sectors_with_dma ({} x {})", lba, request.block_count());
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prdt().offset = m_dma_buffer_page->paddr();
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prdt().size = 512 * request.block_count();
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if (!request.read_from_buffer(request.buffer(), m_dma_buffer_page->paddr().offset(0xc0000000).as_ptr(), 512 * request.block_count())) {
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complete_current_request(AsyncDeviceRequest::MemoryFault);
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return;
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}
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VERIFY(prdt().size <= PAGE_SIZE);
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// Stop bus master
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m_io_group.bus_master_base().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().offset(4).out<u32>(m_prdt_page->paddr().get());
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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ata_access(Direction::Write, slave_request, lba, request.block_count(), capabilities, true);
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// Start bus master
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m_io_group.bus_master_base().out<u8>(0x1);
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ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities);
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}
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void IDEChannel::ata_do_write_sector()
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@ -577,7 +468,7 @@ void IDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
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u32 count = request.block_count();
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dbgln_if(PATA_DEBUG, "IDEChannel: Writing {} sector(s) @ LBA {}", count, start_sector);
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ata_access(Direction::Write, slave_request, start_sector, request.block_count(), capabilities, false);
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ata_access(Direction::Write, slave_request, start_sector, request.block_count(), capabilities);
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ata_do_write_sector();
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}
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}
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