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Kernel: Add PMCCNTR_EL0, Performance Monitors Cycle Count Register
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@ -762,4 +762,19 @@ struct alignas(u64) NZCV {
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};
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};
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static_assert(sizeof(NZCV) == 8);
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static_assert(sizeof(NZCV) == 8);
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// https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/PMCCNTR-EL0--Performance-Monitors-Cycle-Count-Register
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// PMCCNTR_EL0, Performance Monitors Cycle Count Register
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struct alignas(u64) PMCCNTR_EL0 {
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u64 CCNT : 64;
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static inline PMCCNTR_EL0 read()
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{
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PMCCNTR_EL0 pmccntr_el0;
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asm volatile("mrs %[value], pmccntr_el0"
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: [value] "=r"(pmccntr_el0));
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return pmccntr_el0;
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}
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};
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static_assert(sizeof(PMCCNTR_EL0) == 8);
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}
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}
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