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UserspaceEmulator: Implement more SHLD/SHRD variants
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db1929e3ff
commit
897af8b4f7
1 changed files with 33 additions and 10 deletions
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@ -614,7 +614,7 @@ ALWAYS_INLINE static T op_shrd(SoftCPU& cpu, T data, T extra_bits, u8 steps)
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: "=a"(result)
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: "a"(data), "d"(extra_bits), "c"(steps));
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} else if constexpr (sizeof(T) == 2) {
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asm volatile("shrb %%cl, %%dx, %%ax\n"
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asm volatile("shrd %%cl, %%dx, %%ax\n"
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: "=a"(result)
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: "a"(data), "d"(extra_bits), "c"(steps));
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}
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@ -642,7 +642,7 @@ ALWAYS_INLINE static T op_shld(SoftCPU& cpu, T data, T extra_bits, u8 steps)
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: "=a"(result)
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: "a"(data), "d"(extra_bits), "c"(steps));
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} else if constexpr (sizeof(T) == 2) {
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asm volatile("shlb %%cl, %%dx, %%ax\n"
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asm volatile("shld %%cl, %%dx, %%ax\n"
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: "=a"(result)
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: "a"(data), "d"(extra_bits), "c"(steps));
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}
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@ -1665,24 +1665,47 @@ void SoftCPU::SETcc_RM8(const X86::Instruction& insn)
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}
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void SoftCPU::SGDT(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHLD_RM16_reg16_CL(const X86::Instruction& insn)
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{
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insn.modrm().write16(*this, insn, op_shld(*this, insn.modrm().read16(*this, insn), gpr16(insn.reg16()), cl()));
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}
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void SoftCPU::SHLD_RM16_reg16_imm8(const X86::Instruction& insn)
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{
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insn.modrm().write16(*this, insn, op_shld(*this, insn.modrm().read16(*this, insn), gpr16(insn.reg16()), insn.imm8()));
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}
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void SoftCPU::SHLD_RM32_reg32_CL(const X86::Instruction& insn)
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{
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insn.modrm().write32(*this, insn, op_shld(*this, insn.modrm().read32(*this, insn), gpr32(insn.reg32()), cl()));
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}
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void SoftCPU::SHLD_RM32_reg32_imm8(const X86::Instruction& insn)
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{
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insn.modrm().write32(*this, insn, op_shld(*this, gpr32(insn.reg32()), insn.modrm().read32(*this, insn), insn.imm8()));
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insn.modrm().write32(*this, insn, op_shld(*this, insn.modrm().read32(*this, insn), gpr32(insn.reg32()), insn.imm8()));
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}
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DEFINE_GENERIC_SHIFT_ROTATE_INSN_HANDLERS(SHL, op_shl)
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void SoftCPU::SHRD_RM16_reg16_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM16_reg16_imm8(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM32_reg32_CL(const X86::Instruction&) { TODO(); }
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void SoftCPU::SHRD_RM16_reg16_CL(const X86::Instruction& insn)
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{
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insn.modrm().write16(*this, insn, op_shrd(*this, insn.modrm().read16(*this, insn), gpr16(insn.reg16()), cl()));
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}
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void SoftCPU::SHRD_RM16_reg16_imm8(const X86::Instruction& insn)
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{
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insn.modrm().write16(*this, insn, op_shrd(*this, insn.modrm().read16(*this, insn), gpr16(insn.reg16()), insn.imm8()));
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}
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void SoftCPU::SHRD_RM32_reg32_CL(const X86::Instruction& insn)
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{
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insn.modrm().write32(*this, insn, op_shrd(*this, insn.modrm().read32(*this, insn), gpr32(insn.reg32()), cl()));
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}
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void SoftCPU::SHRD_RM32_reg32_imm8(const X86::Instruction& insn)
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{
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insn.modrm().write32(*this, insn, op_shrd(*this, gpr32(insn.reg32()), insn.modrm().read32(*this, insn), insn.imm8()));
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insn.modrm().write32(*this, insn, op_shrd(*this, insn.modrm().read32(*this, insn), gpr32(insn.reg32()), insn.imm8()));
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}
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DEFINE_GENERIC_SHIFT_ROTATE_INSN_HANDLERS(SHR, op_shr)
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