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Kernel: Add some CPU feature flags related to TSC
In case we want to rely more on TSC in time keeping in the future, idk This adds: - RDTSCP, for when the RDTSCP instruction is available - CONSTANT_TSC, for when the TSC has a constant frequency, invariant under things like the CPU boosting its frequency. - NONSTOP_TSC, for when the TSC doesn't pause when the CPU enters sleep states. AMD cpus and newer intel cpus set the INVSTC bit (bit 8 in edx of extended cpuid 0x8000000008), which implies both CONSTANT_TSC and NONSTOP_TSC. Some older intel processors have CONSTANT_TSC but not NONSTOP_TSC; this is set based on cpu model checks. There isn't a ton of documentation on this, so this follows Linux terminology and http://blog.tinola.com/?e=54 CONSTANT_TSC:39b3a79105
NONSTOP_TSC:40fb17152c
qemu disables invtsc (bit 8 in edx of extended cpuid 0x8000000008) by default even if the host cpu supports it. It can be enabled by running with `SERENITY_QEMU_CPU=host,migratable=off` set.
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3 changed files with 41 additions and 12 deletions
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@ -606,15 +606,18 @@ enum class CPUFeature : u32 {
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SMEP = (1 << 6),
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SSE = (1 << 7),
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TSC = (1 << 8),
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UMIP = (1 << 9),
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SEP = (1 << 10),
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SYSCALL = (1 << 11),
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MMX = (1 << 12),
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SSE2 = (1 << 13),
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SSE3 = (1 << 14),
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SSSE3 = (1 << 15),
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SSE4_1 = (1 << 16),
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SSE4_2 = (1 << 17)
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RDTSCP = (1 << 9),
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CONSTANT_TSC = (1 << 10),
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NONSTOP_TSC = (1 << 11),
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UMIP = (1 << 12),
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SEP = (1 << 13),
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SYSCALL = (1 << 14),
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MMX = (1 << 15),
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SSE2 = (1 << 16),
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SSE3 = (1 << 17),
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SSSE3 = (1 << 18),
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SSE4_1 = (1 << 19),
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SSE4_2 = (1 << 20),
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};
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class Thread;
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