mirror of
https://github.com/RGBCube/serenity
synced 2025-05-31 13:28:11 +00:00
Kernel: Add x2APIC support
This allows addressing all cores on more modern processors. For now, we still have a hardcoded limit of 64 due to s_processors being a static array.
This commit is contained in:
Tom
Andreas Kling
parent
123087e235
commit
8a258edfd6
5 changed files with 108 additions and 48 deletions
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@ -34,7 +34,9 @@
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#define APIC_ENABLED (1 << 8)
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#define APIC_BASE_MSR 0x1b
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#define APIC_REGS_MSR_BASE 0x800
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#define APIC_REG_ID 0x20
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#define APIC_REG_EOI 0xb0
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#define APIC_REG_LD 0xd0
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#define APIC_REG_DF 0xe0
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@ -145,27 +147,39 @@ PhysicalAddress APIC::get_base()
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void APIC::set_base(const PhysicalAddress& base)
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{
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MSR msr(APIC_BASE_MSR);
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msr.set(base.get() | 0x800);
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u64 flags = 1 << 11;
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if (m_is_x2)
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flags |= 1 << 10;
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msr.set(base.get() | flags);
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}
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void APIC::write_register(u32 offset, u32 value)
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{
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*reinterpret_cast<volatile u32*>(m_apic_base->vaddr().offset(offset).as_ptr()) = value;
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if (m_is_x2) {
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MSR msr(APIC_REGS_MSR_BASE + (offset >> 4));
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msr.set(value);
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} else {
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*reinterpret_cast<volatile u32*>(m_apic_base->vaddr().offset(offset).as_ptr()) = value;
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}
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}
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u32 APIC::read_register(u32 offset)
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{
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if (m_is_x2) {
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MSR msr(APIC_REGS_MSR_BASE + (offset >> 4));
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return (u32)msr.get();
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}
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return *reinterpret_cast<volatile u32*>(m_apic_base->vaddr().offset(offset).as_ptr());
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}
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void APIC::set_lvt(u32 offset, u8 interrupt)
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{
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write_register(offset, (read_register(offset) & 0xffffffff) | interrupt);
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write_register(offset, read_register(offset) | interrupt);
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}
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void APIC::set_siv(u32 offset, u8 interrupt)
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{
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write_register(offset, (read_register(offset) & 0xffffffff) | interrupt | APIC_ENABLED);
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write_register(offset, read_register(offset) | interrupt | APIC_ENABLED);
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}
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void APIC::wait_for_pending_icr()
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@ -177,8 +191,13 @@ void APIC::wait_for_pending_icr()
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void APIC::write_icr(const ICRReg& icr)
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{
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write_register(APIC_REG_ICR_HIGH, icr.high());
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write_register(APIC_REG_ICR_LOW, icr.low());
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if (m_is_x2) {
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MSR msr(APIC_REGS_MSR_BASE + (APIC_REG_ICR_LOW >> 4));
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msr.set(icr.x2_value());
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} else {
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write_register(APIC_REG_ICR_HIGH, icr.x_high());
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write_register(APIC_REG_ICR_LOW, icr.x_low());
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}
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}
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#define APIC_LVT_TIMER_ONESHOT 0
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@ -224,15 +243,19 @@ UNMAP_AFTER_INIT bool APIC::init_bsp()
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CPUID id(1);
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if ((id.edx() & (1 << 9)) == 0)
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return false;
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if (id.ecx() & (1 << 21))
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m_is_x2 = true;
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PhysicalAddress apic_base = get_base();
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dbgln_if(APIC_DEBUG, "Initializing APIC, base: {}", apic_base);
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dbgln_if(APIC_DEBUG, "Initializing {}APIC, base: {}", m_is_x2 ? "x2" : "x", apic_base);
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set_base(apic_base);
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m_apic_base = MM.allocate_kernel_region(apic_base.page_base(), PAGE_SIZE, {}, Memory::Region::Access::ReadWrite);
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if (!m_apic_base) {
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dbgln("APIC: Failed to allocate memory for APIC base");
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return false;
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if (!m_is_x2) {
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m_apic_base = MM.allocate_kernel_region(apic_base.page_base(), PAGE_SIZE, {}, Memory::Region::Access::ReadWrite);
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if (!m_apic_base) {
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dbgln("APIC: Failed to allocate memory for APIC base");
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return false;
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}
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}
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auto rsdp = ACPI::StaticParsing::find_rsdp();
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@ -254,10 +277,17 @@ UNMAP_AFTER_INIT bool APIC::init_bsp()
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size_t entry_length = madt_entry->length;
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if (madt_entry->type == (u8)ACPI::Structures::MADTEntryType::LocalAPIC) {
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auto* plapic_entry = (const ACPI::Structures::MADTEntries::ProcessorLocalAPIC*)madt_entry;
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dbgln_if(APIC_DEBUG, "APIC: AP found @ MADT entry {}, processor ID: {}, APIC ID: {}, flags: {:#08x}", entry_index, plapic_entry->acpi_processor_id, plapic_entry->apic_id, plapic_entry->flags);
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dbgln_if(APIC_DEBUG, "APIC: AP found @ MADT entry {}, processor ID: {}, xAPIC ID: {}, flags: {:#08x}", entry_index, plapic_entry->acpi_processor_id, plapic_entry->apic_id, plapic_entry->flags);
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m_processor_cnt++;
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if ((plapic_entry->flags & 0x1) != 0)
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m_processor_enabled_cnt++;
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} else if (madt_entry->type == (u8)ACPI::Structures::MADTEntryType::Local_x2APIC) {
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// Only used for APID IDs >= 255
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auto* plx2apic_entry = (const ACPI::Structures::MADTEntries::ProcessorLocalX2APIC*)madt_entry;
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dbgln_if(APIC_DEBUG, "APIC: AP found @ MADT entry {}, processor ID: {}, x2APIC ID: {}, flags: {:#08x}", entry_index, plx2apic_entry->acpi_processor_id, plx2apic_entry->apic_id, plx2apic_entry->flags);
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m_processor_cnt++;
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if ((plx2apic_entry->flags & 0x1) != 0)
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m_processor_enabled_cnt++;
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}
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madt_entry = (ACPI::Structures::MADTEntryHeader*)(VirtualAddress(madt_entry).offset(entry_length).get());
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entries_length -= entry_length;
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@ -357,13 +387,13 @@ UNMAP_AFTER_INIT void APIC::do_boot_aps()
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dbgln_if(APIC_DEBUG, "APIC: Starting {} AP(s)", aps_to_enable);
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// INIT
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write_icr(ICRReg(0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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write_icr({ 0, 0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf });
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IO::delay(10 * 1000);
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr(ICRReg(0x08, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf)); // start execution at P8000
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write_icr({ 0x08, 0, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf }); // start execution at P8000
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IO::delay(200);
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}
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@ -405,17 +435,28 @@ UNMAP_AFTER_INIT void APIC::boot_aps()
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UNMAP_AFTER_INIT void APIC::enable(u32 cpu)
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{
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if (cpu >= 8) {
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// TODO: x2apic support?
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PANIC("SMP support is currently limited to 8 CPUs!");
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VERIFY(m_is_x2 || cpu < 8);
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u32 apic_id;
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if (m_is_x2) {
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dbgln_if(APIC_DEBUG, "Enable x2APIC on CPU #{}", cpu);
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// We need to enable x2 mode on each core independently
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set_base(get_base());
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apic_id = read_register(APIC_REG_ID);
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} else {
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dbgln_if(APIC_DEBUG, "Setting logical xAPIC ID for CPU #{}", cpu);
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// Use the CPU# as logical apic id
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VERIFY(cpu <= 8);
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write_register(APIC_REG_LD, (read_register(APIC_REG_LD) & 0x00ffffff) | (cpu << 24));
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// read it back to make sure it's actually set
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apic_id = read_register(APIC_REG_LD) >> 24;
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}
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// Use the CPU# as logical apic id
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VERIFY(cpu <= 0xff);
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write_register(APIC_REG_LD, (read_register(APIC_REG_LD) & 0x00ffffff) | (cpu << 24)); // TODO: only if not in x2apic mode
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// read it back to make sure it's actually set
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auto apic_id = read_register(APIC_REG_LD) >> 24;
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dbgln_if(APIC_DEBUG, "CPU #{} apic id: {}", cpu, apic_id);
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Processor::current().info().set_apic_id(apic_id);
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dbgln_if(APIC_DEBUG, "Enabling local APIC for CPU #{}, logical APIC ID: {}", cpu, apic_id);
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@ -423,20 +464,23 @@ UNMAP_AFTER_INIT void APIC::enable(u32 cpu)
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if (cpu == 0) {
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SpuriousInterruptHandler::initialize(IRQ_APIC_SPURIOUS);
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// set error interrupt vector
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set_lvt(APIC_REG_LVT_ERR, IRQ_APIC_ERR);
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APICErrInterruptHandler::initialize(IRQ_APIC_ERR);
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// register IPI interrupt vector
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APICIPIInterruptHandler::initialize(IRQ_APIC_IPI);
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}
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if (!m_is_x2) {
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// local destination mode (flat mode), not supported in x2 mode
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write_register(APIC_REG_DF, 0xf0000000);
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}
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// set error interrupt vector
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set_lvt(APIC_REG_LVT_ERR, IRQ_APIC_ERR);
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// set spurious interrupt vector
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set_siv(APIC_REG_SIV, IRQ_APIC_SPURIOUS);
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// local destination mode (flat mode)
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write_register(APIC_REG_DF, 0xf0000000);
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write_register(APIC_REG_LVT_TIMER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_THERMAL, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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write_register(APIC_REG_LVT_PERFORMANCE_COUNTER, APIC_LVT(0, 0) | APIC_LVT_MASKED);
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@ -485,21 +529,21 @@ void APIC::broadcast_ipi()
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{
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dbgln_if(APIC_SMP_DEBUG, "SMP: Broadcast IPI from CPU #{}", Processor::current_id());
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wait_for_pending_icr();
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write_icr(ICRReg(IRQ_APIC_IPI + IRQ_VECTOR_BASE, ICRReg::Fixed, ICRReg::Logical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf));
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write_icr({ IRQ_APIC_IPI + IRQ_VECTOR_BASE, 0xffffffff, ICRReg::Fixed, ICRReg::Logical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf });
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}
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void APIC::send_ipi(u32 cpu)
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{
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dbgln_if(APIC_SMP_DEBUG, "SMP: Send IPI from CPU #{} to CPU #{}", Processor::current_id(), cpu);
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VERIFY(cpu != Processor::current_id());
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VERIFY(cpu < 8);
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VERIFY(cpu < Processor::count());
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wait_for_pending_icr();
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write_icr(ICRReg(IRQ_APIC_IPI + IRQ_VECTOR_BASE, ICRReg::Fixed, ICRReg::Logical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::NoShorthand, cpu));
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write_icr({ IRQ_APIC_IPI + IRQ_VECTOR_BASE, m_is_x2 ? Processor::by_id(cpu).info().apic_id() : cpu, ICRReg::Fixed, m_is_x2 ? ICRReg::Physical : ICRReg::Logical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::NoShorthand });
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}
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UNMAP_AFTER_INIT APICTimer* APIC::initialize_timers(HardwareTimerBase& calibration_timer)
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{
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if (!m_apic_base)
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if (!m_apic_base && !m_is_x2)
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return nullptr;
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// We should only initialize and calibrate the APIC timer once on the BSP!
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