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https://github.com/RGBCube/serenity
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Kernel: Add x2APIC support
This allows addressing all cores on more modern processors. For now, we still have a hardcoded limit of 64 due to s_processors being a static array.
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123087e235
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5 changed files with 108 additions and 48 deletions
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@ -47,11 +47,7 @@ public:
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u32 get_timer_divisor();
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private:
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class ICRReg {
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u32 m_low { 0 };
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u32 m_high { 0 };
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public:
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struct ICRReg {
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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@ -79,14 +75,17 @@ private:
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AllExcludingSelf = 0x3,
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};
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destinationShort, u8 destination = 0)
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: m_low(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destinationShort << 18))
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, m_high((u32)destination << 24)
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{
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}
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u8 vector { 0 };
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u32 destination { 0 };
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DeliveryMode delivery_mode { DeliveryMode::Fixed };
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DestinationMode destination_mode { DestinationMode::Physical };
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Level level { Level::DeAssert };
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TriggerMode trigger_mode { TriggerMode::Edge };
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DestinationShorthand destination_short { DestinationShorthand::NoShorthand };
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u32 low() const { return m_low; }
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u32 high() const { return m_high; }
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u32 x_low() const { return (u32)vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination_short << 18); }
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u32 x_high() const { return destination << 24; }
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u64 x2_value() const { return ((u64)destination << 32) | x_low(); }
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};
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OwnPtr<Memory::Region> m_apic_base;
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@ -97,9 +96,10 @@ private:
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u32 m_processor_cnt { 0 };
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u32 m_processor_enabled_cnt { 0 };
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APICTimer* m_apic_timer { nullptr };
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bool m_is_x2 { false };
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static PhysicalAddress get_base();
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static void set_base(const PhysicalAddress& base);
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void set_base(const PhysicalAddress& base);
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void write_register(u32 offset, u32 value);
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u32 read_register(u32 offset);
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void set_lvt(u32 offset, u8 interrupt);
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