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Kernel/PCI: Introduce a new ECAM access mechanism
Now the kernel supports 2 ECAM access methods. MMIOAccess was renamed to WindowedMMIOAccess and is what we had until now - each device that is detected on boot is assigned to a memory-mapped window, so IO operations on multiple devices can occur simultaneously due to creating multiple virtual mappings, hence the name is a memory-mapped window. This commit adds a new class called MMIOAccess (not to be confused with the old MMIOAccess class). This class creates one memory-mapped window. On each IO operation on a configuration space of a device, it maps the requested PCI bus region to that window. Therefore it holds a SpinLock during the operation to ensure that no other PCI bus region was mapped during the call. A user can choose to either use PCI ECAM with memory-mapped window for each device, or for an entire bus. By default, the kernel prefers to map the entire PCI bus region.
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parent
441e374396
commit
8abbb7e090
11 changed files with 320 additions and 100 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -33,52 +33,35 @@
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namespace Kernel {
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namespace PCI {
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class MMIOSegment {
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public:
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MMIOSegment(PhysicalAddress, u8, u8);
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u8 get_start_bus() const;
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u8 get_end_bus() const;
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size_t get_size() const;
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PhysicalAddress get_paddr() const;
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#define MEMORY_RANGE_PER_BUS (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS)
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private:
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PhysicalAddress m_base_addr;
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u8 m_start_bus;
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u8 m_end_bus;
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};
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#define PCI_MMIO_CONFIG_SPACE_SIZE 4096
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UNMAP_AFTER_INIT DeviceConfigurationSpaceMapping::DeviceConfigurationSpaceMapping(Address device_address, const MMIOSegment& mmio_segment)
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: m_device_address(device_address)
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, m_mapped_region(MM.allocate_kernel_region(page_round_up(PCI_MMIO_CONFIG_SPACE_SIZE), "PCI MMIO Device Access", Region::Access::Read | Region::Access::Write).release_nonnull())
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{
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PhysicalAddress segment_lower_addr = mmio_segment.get_paddr();
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PhysicalAddress device_physical_mmio_space = segment_lower_addr.offset(
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PCI_MMIO_CONFIG_SPACE_SIZE * m_device_address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * m_device_address.device() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS) * (m_device_address.bus() - mmio_segment.get_start_bus()));
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m_mapped_region->physical_page_slot(0) = PhysicalPage::create(device_physical_mmio_space, false, false);
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m_mapped_region->remap();
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}
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uint32_t MMIOAccess::segment_count() const
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u32 MMIOAccess::segment_count() const
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{
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return m_segments.size();
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}
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uint8_t MMIOAccess::segment_start_bus(u32 seg) const
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u8 MMIOAccess::segment_start_bus(u32 seg) const
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{
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auto segment = m_segments.get(seg);
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VERIFY(segment.has_value());
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return segment.value().get_start_bus();
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}
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uint8_t MMIOAccess::segment_end_bus(u32 seg) const
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u8 MMIOAccess::segment_end_bus(u32 seg) const
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{
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auto segment = m_segments.get(seg);
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VERIFY(segment.has_value());
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return segment.value().get_end_bus();
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}
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PhysicalAddress MMIOAccess::determine_memory_mapped_bus_region(u32 segment, u8 bus) const
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{
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VERIFY(bus >= segment_start_bus(segment) && bus <= segment_end_bus(segment));
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auto seg = m_segments.get(segment);
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VERIFY(seg.has_value());
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return seg.value().get_paddr().offset(MEMORY_RANGE_PER_BUS * (bus - seg.value().get_start_bus()));
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}
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UNMAP_AFTER_INIT void MMIOAccess::initialize(PhysicalAddress mcfg)
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{
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if (!Access::is_initialized()) {
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@ -118,77 +101,78 @@ UNMAP_AFTER_INIT MMIOAccess::MMIOAccess(PhysicalAddress p_mcfg)
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dmesgln("PCI: MMIO segments: {}", m_segments.size());
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InterruptDisabler disabler;
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VERIFY(m_segments.contains(0));
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// Note: we need to map this region before enumerating the hardware and adding
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// PCI::PhysicalID objects to the vector, because get_capabilities calls
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// PCI::read16 which will need this region to be mapped.
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m_mapped_region = MM.allocate_kernel_region(determine_memory_mapped_bus_region(0, m_segments.get(0).value().get_start_bus()), MEMORY_RANGE_PER_BUS, "PCI ECAM", Region::Access::Read | Region::Access::Write);
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dmesgln("PCI ECAM Mapped region @ {}", m_mapped_region->vaddr());
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enumerate_hardware([&](const Address& address, ID id) {
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m_mapped_device_regions.append(make<DeviceConfigurationSpaceMapping>(address, m_segments.get(address.seg()).value()));
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m_physical_ids.append({ address, id, get_capabilities(address) });
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dbgln_if(PCI_DEBUG, "PCI: Mapping device @ pci ({}) {} {}", address, m_mapped_device_regions.last().vaddr(), m_mapped_device_regions.last().paddr());
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});
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}
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Optional<VirtualAddress> MMIOAccess::get_device_configuration_space(Address address)
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void MMIOAccess::map_bus_region(u32 segment, u8 bus)
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{
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dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
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for (auto& mapping : m_mapped_device_regions) {
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auto checked_address = mapping.address();
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dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Check if {} was requested", checked_address);
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if (address.seg() == checked_address.seg()
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&& address.bus() == checked_address.bus()
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&& address.device() == checked_address.device()
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&& address.function() == checked_address.function()) {
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dbgln_if(PCI_DEBUG, "PCI Device Configuration Space Mapping: Found {}", checked_address);
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return mapping.vaddr();
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}
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}
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VERIFY(m_access_lock.is_locked());
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if (m_mapped_bus == bus)
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return;
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m_mapped_region = MM.allocate_kernel_region(determine_memory_mapped_bus_region(segment, bus), MEMORY_RANGE_PER_BUS, "PCI ECAM", Region::Access::Read | Region::Access::Write);
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}
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dbgln_if(PCI_DEBUG, "PCI: No device configuration space found for {}", address);
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return {};
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VirtualAddress MMIOAccess::get_device_configuration_space(Address address)
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{
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VERIFY(m_access_lock.is_locked());
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dbgln_if(PCI_DEBUG, "PCI: Getting device configuration space for {}", address);
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map_bus_region(address.seg(), address.bus());
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return m_mapped_region->vaddr().offset(PCI_MMIO_CONFIG_SPACE_SIZE * address.function() + (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE) * address.device());
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}
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u8 MMIOAccess::read8_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ScopedSpinLock lock(m_access_lock);
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VERIFY(field <= 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 8-bit field {:#08x} for {}", field, address);
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return *((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
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return *((volatile u8*)(get_device_configuration_space(address).get() + (field & 0xfff)));
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}
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u16 MMIOAccess::read16_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ScopedSpinLock lock(m_access_lock);
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VERIFY(field < 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 16-bit field {:#08x} for {}", field, address);
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return *((u16*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
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return *((volatile u16*)(get_device_configuration_space(address).get() + (field & 0xfff)));
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}
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u32 MMIOAccess::read32_field(Address address, u32 field)
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{
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InterruptDisabler disabler;
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ScopedSpinLock lock(m_access_lock);
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VERIFY(field <= 0xffc);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Reading 32-bit field {:#08x} for {}", field, address);
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return *((u32*)(get_device_configuration_space(address).value().get() + (field & 0xfff)));
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return *((volatile u32*)(get_device_configuration_space(address).get() + (field & 0xfff)));
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}
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void MMIOAccess::write8_field(Address address, u32 field, u8 value)
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{
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InterruptDisabler disabler;
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ScopedSpinLock lock(m_access_lock);
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VERIFY(field <= 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 8-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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*((u8*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
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*((volatile u8*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
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}
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void MMIOAccess::write16_field(Address address, u32 field, u16 value)
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{
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InterruptDisabler disabler;
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ScopedSpinLock lock(m_access_lock);
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VERIFY(field < 0xfff);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 16-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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*((u16*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
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*((volatile u16*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
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}
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void MMIOAccess::write32_field(Address address, u32 field, u32 value)
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{
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InterruptDisabler disabler;
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ScopedSpinLock lock(m_access_lock);
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VERIFY(field <= 0xffc);
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dbgln_if(PCI_DEBUG, "PCI: MMIO Writing 32-bit field {:#08x}, value={:#02x} for {}", field, value, address);
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*((u32*)(get_device_configuration_space(address).value().get() + (field & 0xfff))) = value;
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*((volatile u32*)(get_device_configuration_space(address).get() + (field & 0xfff))) = value;
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}
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void MMIOAccess::enumerate_hardware(Function<void(Address, ID)> callback)
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@ -210,29 +194,29 @@ void MMIOAccess::enumerate_hardware(Function<void(Address, ID)> callback)
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}
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}
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MMIOSegment::MMIOSegment(PhysicalAddress segment_base_addr, u8 start_bus, u8 end_bus)
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MMIOAccess::MMIOSegment::MMIOSegment(PhysicalAddress segment_base_addr, u8 start_bus, u8 end_bus)
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: m_base_addr(segment_base_addr)
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, m_start_bus(start_bus)
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, m_end_bus(end_bus)
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{
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}
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u8 MMIOSegment::get_start_bus() const
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u8 MMIOAccess::MMIOSegment::get_start_bus() const
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{
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return m_start_bus;
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}
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u8 MMIOSegment::get_end_bus() const
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u8 MMIOAccess::MMIOSegment::get_end_bus() const
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{
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return m_end_bus;
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}
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size_t MMIOSegment::get_size() const
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size_t MMIOAccess::MMIOSegment::get_size() const
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{
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return (PCI_MMIO_CONFIG_SPACE_SIZE * PCI_MAX_FUNCTIONS_PER_DEVICE * PCI_MAX_DEVICES_PER_BUS * (get_end_bus() - get_start_bus()));
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}
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PhysicalAddress MMIOSegment::get_paddr() const
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PhysicalAddress MMIOAccess::MMIOSegment::get_paddr() const
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{
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return m_base_addr;
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}
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