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Kernel/Storage: Add support for non-bus mastering IDE controllers
Although unlikely to happen, a user can have an IDE controller that doesn't support bus master capability. If that's the case, we need to check for this, and create an IDEChannel (not BMIDEChannel) to allow IO operations with the controller.
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parent
833a6bd047
commit
8b446fb579
5 changed files with 40 additions and 24 deletions
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@ -74,7 +74,8 @@ void BMIDEChannel::handle_irq(const RegisterState&)
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m_entropy_source.add_random_event(status);
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u8 bstatus = m_io_group.bus_master_base().offset(2).in<u8>();
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VERIFY(m_io_group.bus_master_base().has_value());
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u8 bstatus = m_io_group.bus_master_base().value().offset(2).in<u8>();
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if (!(bstatus & 0x4)) {
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// interrupt not from this device, ignore
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dbgln_if(PATA_DEBUG, "BMIDEChannel: ignore interrupt");
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@ -131,7 +132,8 @@ void BMIDEChannel::complete_current_request(AsyncDeviceRequest::RequestResult re
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}
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// I read somewhere that this may trigger a cache flush so let's do it.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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VERIFY(m_io_group.bus_master_base().has_value());
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
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}
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lock.unlock();
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@ -155,20 +157,20 @@ void BMIDEChannel::ata_write_sectors(bool slave_request, u16 capabilities)
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}
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VERIFY(prdt().size <= PAGE_SIZE);
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VERIFY(m_io_group.bus_master_base().has_value());
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// Stop bus master
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m_io_group.bus_master_base().out<u8>(0);
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m_io_group.bus_master_base().value().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().offset(4).out<u32>(m_prdt_page->paddr().get());
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m_io_group.bus_master_base().value().offset(4).out<u32>(m_prdt_page->paddr().get());
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
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ata_access(Direction::Write, slave_request, lba, request.block_count(), capabilities);
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// Start bus master
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m_io_group.bus_master_base().out<u8>(0x1);
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m_io_group.bus_master_base().value().out<u8>(0x1);
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}
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void BMIDEChannel::send_ata_io_command(LBAMode lba_mode, Direction direction) const
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@ -192,22 +194,23 @@ void BMIDEChannel::ata_read_sectors(bool slave_request, u16 capabilities)
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VERIFY(prdt().size <= PAGE_SIZE);
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VERIFY(m_io_group.bus_master_base().has_value());
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// Stop bus master
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m_io_group.bus_master_base().out<u8>(0);
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m_io_group.bus_master_base().value().out<u8>(0);
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// Write the PRDT location
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m_io_group.bus_master_base().offset(4).out(m_prdt_page->paddr().get());
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m_io_group.bus_master_base().value().offset(4).out(m_prdt_page->paddr().get());
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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m_io_group.bus_master_base().offset(2).out<u8>(m_io_group.bus_master_base().offset(2).in<u8>() | 0x6);
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m_io_group.bus_master_base().value().offset(2).out<u8>(m_io_group.bus_master_base().value().offset(2).in<u8>() | 0x6);
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// Set transfer direction
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m_io_group.bus_master_base().out<u8>(0x8);
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m_io_group.bus_master_base().value().out<u8>(0x8);
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ata_access(Direction::Read, slave_request, lba, request.block_count(), capabilities);
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// Start bus master
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m_io_group.bus_master_base().out<u8>(0x9);
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m_io_group.bus_master_base().value().out<u8>(0x9);
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}
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}
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