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Kernel: Reorganize Arch/x86 directory to Arch/x86_64 after i686 removal
No functional change.
This commit is contained in:
Liav A
Andreas Kling
parent
5ff318cf3a
commit
91db482ad3
129 changed files with 482 additions and 1116 deletions
242
Kernel/Arch/x86_64/CPUID.h
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242
Kernel/Arch/x86_64/CPUID.h
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/*
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* Copyright (c) 2018-2021, Andreas Kling <kling@serenityos.org>
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* Copyright (c) 2022, Linus Groh <linusg@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/ArbitrarySizedEnum.h>
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#include <AK/Types.h>
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#include <AK/UFixedBigInt.h>
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#include <AK/Platform.h>
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VALIDATE_IS_X86()
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namespace Kernel {
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class CPUID {
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public:
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explicit CPUID(u32 function, u32 ecx = 0)
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{
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asm volatile("cpuid"
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: "=a"(m_eax), "=b"(m_ebx), "=c"(m_ecx), "=d"(m_edx)
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: "a"(function), "c"(ecx));
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}
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u32 eax() const { return m_eax; }
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u32 ebx() const { return m_ebx; }
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u32 ecx() const { return m_ecx; }
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u32 edx() const { return m_edx; }
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private:
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u32 m_eax { 0xffffffff };
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u32 m_ebx { 0xffffffff };
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u32 m_ecx { 0xffffffff };
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u32 m_edx { 0xffffffff };
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};
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AK_MAKE_ARBITRARY_SIZED_ENUM(CPUFeature, u256,
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/* EAX=1, ECX */ //
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SSE3 = CPUFeature(1u) << 0u, // Streaming SIMD Extensions 3
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PCLMULQDQ = CPUFeature(1u) << 1u, // PCLMULDQ Instruction
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DTES64 = CPUFeature(1u) << 2u, // 64-Bit Debug Store
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MONITOR = CPUFeature(1u) << 3u, // MONITOR/MWAIT Instructions
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DS_CPL = CPUFeature(1u) << 4u, // CPL Qualified Debug Store
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VMX = CPUFeature(1u) << 5u, // Virtual Machine Extensions
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SMX = CPUFeature(1u) << 6u, // Safer Mode Extensions
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EST = CPUFeature(1u) << 7u, // Enhanced Intel SpeedStep® Technology
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TM2 = CPUFeature(1u) << 8u, // Thermal Monitor 2
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SSSE3 = CPUFeature(1u) << 9u, // Supplemental Streaming SIMD Extensions 3
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CNXT_ID = CPUFeature(1u) << 10u, // L1 Context ID
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SDBG = CPUFeature(1u) << 11u, // Silicon Debug (IA32_DEBUG_INTERFACE MSR)
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FMA = CPUFeature(1u) << 12u, // Fused Multiply Add
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CX16 = CPUFeature(1u) << 13u, // CMPXCHG16B Instruction
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XTPR = CPUFeature(1u) << 14u, // xTPR Update Control
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PDCM = CPUFeature(1u) << 15u, // Perfmon and Debug Capability (IA32_PERF_CAPABILITIES MSR)
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/* ECX Bit 16 */ // Reserved
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PCID = CPUFeature(1u) << 17u, // Process Context Identifiers
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DCA = CPUFeature(1u) << 18u, // Direct Cache Access
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SSE4_1 = CPUFeature(1u) << 19u, // Streaming SIMD Extensions 4.1
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SSE4_2 = CPUFeature(1u) << 20u, // Streaming SIMD Extensions 4.2
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X2APIC = CPUFeature(1u) << 21u, // Extended xAPIC Support
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MOVBE = CPUFeature(1u) << 22u, // MOVBE Instruction
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POPCNT = CPUFeature(1u) << 23u, // POPCNT Instruction
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TSC_DEADLINE = CPUFeature(1u) << 24u, // Time Stamp Counter Deadline
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AES = CPUFeature(1u) << 25u, // AES Instruction Extensions
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XSAVE = CPUFeature(1u) << 26u, // XSAVE/XSTOR States
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OSXSAVE = CPUFeature(1u) << 27u, // OS-Enabled Extended State Management
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AVX = CPUFeature(1u) << 28u, // Advanced Vector Extensions
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F16C = CPUFeature(1u) << 29u, // 16-bit floating-point conversion instructions
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RDRAND = CPUFeature(1u) << 30u, // RDRAND Instruction
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HYPERVISOR = CPUFeature(1u) << 31u, // Hypervisor present (always zero on physical CPUs)
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/* EAX=1, EDX */ //
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FPU = CPUFeature(1u) << 32u, // Floating-point Unit On-Chip
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VME = CPUFeature(1u) << 33u, // Virtual Mode Extension
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DE = CPUFeature(1u) << 34u, // Debugging Extension
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PSE = CPUFeature(1u) << 35u, // Page Size Extension
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TSC = CPUFeature(1u) << 36u, // Time Stamp Counter
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MSR = CPUFeature(1u) << 37u, // Model Specific Registers
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PAE = CPUFeature(1u) << 38u, // Physical Address Extension
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MCE = CPUFeature(1u) << 39u, // Machine-Check Exception
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CX8 = CPUFeature(1u) << 40u, // CMPXCHG8 Instruction
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APIC = CPUFeature(1u) << 41u, // On-chip APIC Hardware
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/* EDX Bit 10 */ // Reserved
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SEP = CPUFeature(1u) << 43u, // Fast System Call
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MTRR = CPUFeature(1u) << 44u, // Memory Type Range Registers
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PGE = CPUFeature(1u) << 45u, // Page Global Enable
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MCA = CPUFeature(1u) << 46u, // Machine-Check Architecture
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CMOV = CPUFeature(1u) << 47u, // Conditional Move Instruction
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PAT = CPUFeature(1u) << 48u, // Page Attribute Table
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PSE36 = CPUFeature(1u) << 49u, // 36-bit Page Size Extension
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PSN = CPUFeature(1u) << 50u, // Processor serial number is present and enabled
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CLFLUSH = CPUFeature(1u) << 51u, // CLFLUSH Instruction
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/* EDX Bit 20 */ // Reserved
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DS = CPUFeature(1u) << 53u, // CLFLUSH Instruction
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ACPI = CPUFeature(1u) << 54u, // CLFLUSH Instruction
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MMX = CPUFeature(1u) << 55u, // CLFLUSH Instruction
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FXSR = CPUFeature(1u) << 56u, // CLFLUSH Instruction
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SSE = CPUFeature(1u) << 57u, // Streaming SIMD Extensions
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SSE2 = CPUFeature(1u) << 58u, // Streaming SIMD Extensions 2
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SS = CPUFeature(1u) << 59u, // Self-Snoop
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HTT = CPUFeature(1u) << 60u, // Multi-Threading
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TM = CPUFeature(1u) << 61u, // Thermal Monitor
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IA64 = CPUFeature(1u) << 62u, // IA64 processor emulating x86
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PBE = CPUFeature(1u) << 63u, // Pending Break Enable
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/* EAX=7, EBX */ //
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FSGSBASE = CPUFeature(1u) << 64u, // Access to base of %fs and %gs
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TSC_ADJUST = CPUFeature(1u) << 65u, // IA32_TSC_ADJUST MSR
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SGX = CPUFeature(1u) << 66u, // Software Guard Extensions
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BMI1 = CPUFeature(1u) << 67u, // Bit Manipulation Instruction Set 1
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HLE = CPUFeature(1u) << 68u, // TSX Hardware Lock Elision
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AVX2 = CPUFeature(1u) << 69u, // Advanced Vector Extensions 2
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FDP_EXCPTN_ONLY = CPUFeature(1u) << 70u, // FDP_EXCPTN_ONLY
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SMEP = CPUFeature(1u) << 71u, // Supervisor Mode Execution Protection
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BMI2 = CPUFeature(1u) << 72u, // Bit Manipulation Instruction Set 2
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ERMS = CPUFeature(1u) << 73u, // Enhanced REP MOVSB/STOSB
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INVPCID = CPUFeature(1u) << 74u, // INVPCID Instruction
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RTM = CPUFeature(1u) << 75u, // TSX Restricted Transactional Memory
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PQM = CPUFeature(1u) << 76u, // Platform Quality of Service Monitoring
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ZERO_FCS_FDS = CPUFeature(1u) << 77u, // FPU CS and FPU DS deprecated
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MPX = CPUFeature(1u) << 78u, // Intel MPX (Memory Protection Extensions)
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PQE = CPUFeature(1u) << 79u, // Platform Quality of Service Enforcement
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AVX512_F = CPUFeature(1u) << 80u, // AVX-512 Foundation
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AVX512_DQ = CPUFeature(1u) << 81u, // AVX-512 Doubleword and Quadword Instructions
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RDSEED = CPUFeature(1u) << 82u, // RDSEED Instruction
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ADX = CPUFeature(1u) << 83u, // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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SMAP = CPUFeature(1u) << 84u, // Supervisor Mode Access Prevention
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AVX512_IFMA = CPUFeature(1u) << 85u, // AVX-512 Integer Fused Multiply-Add Instructions
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PCOMMIT = CPUFeature(1u) << 86u, // PCOMMIT Instruction
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CLFLUSHOPT = CPUFeature(1u) << 87u, // CLFLUSHOPT Instruction
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CLWB = CPUFeature(1u) << 88u, // CLWB Instruction
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INTEL_PT = CPUFeature(1u) << 89u, // Intel Processor Tracing
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AVX512_PF = CPUFeature(1u) << 90u, // AVX-512 Prefetch Instructions
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AVX512_ER = CPUFeature(1u) << 91u, // AVX-512 Exponential and Reciprocal Instructions
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AVX512_CD = CPUFeature(1u) << 92u, // AVX-512 Conflict Detection Instructions
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SHA = CPUFeature(1u) << 93u, // Intel SHA Extensions
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AVX512_BW = CPUFeature(1u) << 94u, // AVX-512 Byte and Word Instructions
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AVX512_VL = CPUFeature(1u) << 95u, // AVX-512 Vector Length Extensions
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/* EAX=7, ECX */ //
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PREFETCHWT1 = CPUFeature(1u) << 96u, // PREFETCHWT1 Instruction
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AVX512_VBMI = CPUFeature(1u) << 97u, // AVX-512 Vector Bit Manipulation Instructions
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UMIP = CPUFeature(1u) << 98u, // UMIP
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PKU = CPUFeature(1u) << 99u, // Memory Protection Keys for User-mode pages
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OSPKE = CPUFeature(1u) << 100u, // PKU enabled by OS
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WAITPKG = CPUFeature(1u) << 101u, // Timed pause and user-level monitor/wait
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AVX512_VBMI2 = CPUFeature(1u) << 102u, // AVX-512 Vector Bit Manipulation Instructions 2
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CET_SS = CPUFeature(1u) << 103u, // Control Flow Enforcement (CET) Shadow Stack
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GFNI = CPUFeature(1u) << 104u, // Galois Field Instructions
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VAES = CPUFeature(1u) << 105u, // Vector AES instruction set (VEX-256/EVEX)
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VPCLMULQDQ = CPUFeature(1u) << 106u, // CLMUL instruction set (VEX-256/EVEX)
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AVX512_VNNI = CPUFeature(1u) << 107u, // AVX-512 Vector Neural Network Instructions
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AVX512_BITALG = CPUFeature(1u) << 108u, // AVX-512 BITALG Instructions
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TME_EN = CPUFeature(1u) << 109u, // IA32_TME related MSRs are supported
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AVX512_VPOPCNTDQ = CPUFeature(1u) << 110u, // AVX-512 Vector Population Count Double and Quad-word
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/* ECX Bit 15 */ // Reserved
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INTEL_5_LEVEL_PAGING = CPUFeature(1u) << 112u, // Intel 5-Level Paging
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RDPID = CPUFeature(1u) << 113u, // RDPID Instruction
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KL = CPUFeature(1u) << 114u, // Key Locker
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/* ECX Bit 24 */ // Reserved
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CLDEMOTE = CPUFeature(1u) << 116u, // Cache Line Demote
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/* ECX Bit 26 */ // Reserved
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MOVDIRI = CPUFeature(1u) << 118u, // MOVDIRI Instruction
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MOVDIR64B = CPUFeature(1u) << 119u, // MOVDIR64B Instruction
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ENQCMD = CPUFeature(1u) << 120u, // ENQCMD Instruction
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SGX_LC = CPUFeature(1u) << 121u, // SGX Launch Configuration
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PKS = CPUFeature(1u) << 122u, // Protection Keys for Supervisor-Mode Pages
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/* EAX=7, EDX */ //
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/* ECX Bit 0-1 */ // Reserved
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AVX512_4VNNIW = CPUFeature(1u) << 125u, // AVX-512 4-register Neural Network Instructions
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AVX512_4FMAPS = CPUFeature(1u) << 126u, // AVX-512 4-register Multiply Accumulation Single precision
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FSRM = CPUFeature(1u) << 127u, // Fast Short REP MOVSB
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/* ECX Bit 5-7 */ // Reserved
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AVX512_VP2INTERSECT = CPUFeature(1u) << 131u, // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions
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SRBDS_CTRL = CPUFeature(1u) << 132u, // Special Register Buffer Data Sampling Mitigations
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MD_CLEAR = CPUFeature(1u) << 133u, // VERW instruction clears CPU buffers
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RTM_ALWAYS_ABORT = CPUFeature(1u) << 134u, // All TSX transactions are aborted
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/* ECX Bit 12 */ // Reserved
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TSX_FORCE_ABORT = CPUFeature(1u) << 136u, // TSX_FORCE_ABORT MSR
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SERIALIZE = CPUFeature(1u) << 137u, // Serialize instruction execution
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HYBRID = CPUFeature(1u) << 138u, // Mixture of CPU types in processor topology
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TSXLDTRK = CPUFeature(1u) << 139u, // TSX suspend load address tracking
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/* ECX Bit 17 */ // Reserved
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PCONFIG = CPUFeature(1u) << 141u, // Platform configuration (Memory Encryption Technologies Instructions)
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LBR = CPUFeature(1u) << 142u, // Architectural Last Branch Records
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CET_IBT = CPUFeature(1u) << 143u, // Control flow enforcement (CET) indirect branch tracking
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/* ECX Bit 21 */ // Reserved
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AMX_BF16 = CPUFeature(1u) << 145u, // Tile computation on bfloat16 numbers
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AVX512_FP16 = CPUFeature(1u) << 146u, // AVX512-FP16 half-precision floating-point instructions
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AMX_TILE = CPUFeature(1u) << 147u, // Tile architecture
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AMX_INT8 = CPUFeature(1u) << 148u, // Tile computation on 8-bit integers
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SPEC_CTRL = CPUFeature(1u) << 149u, // Speculation Control
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STIBP = CPUFeature(1u) << 150u, // Single Thread Indirect Branch Predictor
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L1D_FLUSH = CPUFeature(1u) << 151u, // IA32_FLUSH_CMD MSR
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IA32_ARCH_CAPABILITIES = CPUFeature(1u) << 152u, // IA32_ARCH_CAPABILITIES MSR
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IA32_CORE_CAPABILITIES = CPUFeature(1u) << 153u, // IA32_CORE_CAPABILITIES MSR
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SSBD = CPUFeature(1u) << 154u, // Speculative Store Bypass Disable
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/* EAX=80000001h, ECX */ //
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LAHF_LM = CPUFeature(1u) << 155u, // LAHF/SAHF in long mode
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CMP_LEGACY = CPUFeature(1u) << 156u, // Hyperthreading not valid
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SVM = CPUFeature(1u) << 157u, // Secure Virtual Machine
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EXTAPIC = CPUFeature(1u) << 158u, // Extended APIC Space
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CR8_LEGACY = CPUFeature(1u) << 159u, // CR8 in 32-bit mode
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ABM = CPUFeature(1u) << 160u, // Advanced Bit Manipulation
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SSE4A = CPUFeature(1u) << 161u, // SSE4a
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MISALIGNSSE = CPUFeature(1u) << 162u, // Misaligned SSE Mode
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_3DNOWPREFETCH = CPUFeature(1u) << 163u, // PREFETCH and PREFETCHW Instructions
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OSVW = CPUFeature(1u) << 164u, // OS Visible Workaround
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IBS = CPUFeature(1u) << 165u, // Instruction Based Sampling
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XOP = CPUFeature(1u) << 166u, // XOP instruction set
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SKINIT = CPUFeature(1u) << 167u, // SKINIT/STGI Instructions
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WDT = CPUFeature(1u) << 168u, // Watchdog timer
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LWP = CPUFeature(1u) << 169u, // Light Weight Profiling
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FMA4 = CPUFeature(1u) << 170u, // FMA4 instruction set
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TCE = CPUFeature(1u) << 171u, // Translation Cache Extension
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NODEID_MSR = CPUFeature(1u) << 172u, // NodeID MSR
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TBM = CPUFeature(1u) << 173u, // Trailing Bit Manipulation
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TOPOEXT = CPUFeature(1u) << 174u, // Topology Extensions
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PERFCTR_CORE = CPUFeature(1u) << 175u, // Core Performance Counter Extensions
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PERFCTR_NB = CPUFeature(1u) << 176u, // NB Performance Counter Extensions
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DBX = CPUFeature(1u) << 177u, // Data Breakpoint Extensions
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PERFTSC = CPUFeature(1u) << 178u, // Performance TSC
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PCX_L2I = CPUFeature(1u) << 179u, // L2I Performance Counter Extensions
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/* EAX=80000001h, EDX */ //
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SYSCALL = CPUFeature(1u) << 180u, // SYSCALL/SYSRET Instructions
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MP = CPUFeature(1u) << 181u, // Multiprocessor Capable
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NX = CPUFeature(1u) << 182u, // NX bit
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MMXEXT = CPUFeature(1u) << 183u, // Extended MMX
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FXSR_OPT = CPUFeature(1u) << 184u, // FXSAVE/FXRSTOR Optimizations
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PDPE1GB = CPUFeature(1u) << 185u, // Gigabyte Pages
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RDTSCP = CPUFeature(1u) << 186u, // RDTSCP Instruction
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LM = CPUFeature(1u) << 187u, // Long Mode
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_3DNOWEXT = CPUFeature(1u) << 188u, // Extended 3DNow!
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_3DNOW = CPUFeature(1u) << 189u, // 3DNow!
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/* EAX=80000007h, EDX */ //
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CONSTANT_TSC = CPUFeature(1u) << 190u, // Invariant TSC
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NONSTOP_TSC = CPUFeature(1u) << 191u, // Invariant TSC
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__End = CPUFeature(1u) << 255u);
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StringView cpu_feature_to_string_view(CPUFeature::Type const&);
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}
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